A tunable triode-MOSFET transconductor and its application to g(m)-C filters

A linear, tunable CMOS transconductance stage is introduced. Drain voltage of the input transistor operating in triode region is settled by a regulation loop and a first-order linear relationship between g(m) and a de bias voltage is achieved. In addition to easy tuning, this technique offers circuit simplicity, wide dynamic range, high input and output impedances and low consumption. The transconductor is presented on both single-ended and fully-differential versions. A 3rd-order elliptical low-pass g(m)-C filter with a nominal roll-off frequency of 2MHz is used as one example for the many applications of the proposed transconductor. SPICE data describe circuits performances and filter tunabilily Passband is tuned at a rate of 2.36KHz/mV and good linearity is indicated by a 0.89% THD for an 800mV(p-p) balanced-driven input.

A low-voltage triode-MOSFET four-quadrant multiplier with optimized current-efficiency

A low-voltage, low-power four-quadrant analog multiplier with optimized current-efficiency is presented. Its core corresponds to a pseudodifferential cascode, gain-boosting triode-transconductor. According to a low-voltage 1.2μm CMOS n-well process, operand differential-amplitudes are 1.0Vpp and 0.32Vpp for a 1.3V-supply. Common-mode voltages are properly chosen to maximize current-efficiency to 58%. Total quiescent dissipation is 260μW. A range of PSPICE simulation supports theoretical analysis. Excellent linearity is observed on dc characteristic. Assuming a ±0.5% mismatch on (W/L) and VTH THD at full-scale is 0.93% and 1.42%, for output frequencies of 1MHz and 10MHz, respectively.

A low-voltage wide-swing programmable-gain current amplifier

A CMOS low-voltage, wide-swing continuous-time current amplifier is presented. Exhibiting an open-loop architecture, the circuit is composed of transresistance and transconductance stages built upon triode-operating transistors. In addition to an extended dynamic range, the current gain can be programmed within good accuracy by a rapport involving only transistor geometries and tuning biases. Low temperature-drift on gain setting is then expected.In accordance with a 0.35 mum n-well CMOS fabrication process and a single 1.1 V-supply, a balanced current-amplifier is designed for a programmable gain-range of 6 - 34 dB and optimized with respect to dynamic range. Simulated results from PSPICE and Bsim3v3 models indicate, for a 100 muA(pp)-output current, a THD of 0.96 and 1.87% at 1 KHz and 100 KHz, respectively. Input noise is 120 pArootHz @ 10 Hz, with S/N = 63.2 dB @ 1%-THD. At maximum gain, total quiescent consumption is 334 muW. Measurements from a prototyped amplifier reveal a gain-interval of 4.8-33.1 dB and a maximum current swing of 120 muA(pp). The current-amplifier bandwidth is above 1 MHz.

A linearly-tunable OTA-C sinusoidal oscillator for low-voltage applications

A low-voltage, low-power OTA-C sinusoidal oscillator based on a triode-MOSFET transconductor is here discussed. The classical quadrature model is employed and the transconductor inherent nonlinear characteristic with input voltage is used as the amplitude-stabilization element. An external bias VTUNE linearly adjusts the oscillation frequency. According to a standard 0.8μm CMOS n-well process, a prototype was integrated, with an effective area of 0.28mm2. Experimental data validate the theoretical analysis. For a single 1.8V-supply and 100mV≤VTUNE≤250mV, the oscillation frequency fo ranges from 0.50MHz to 1.125MHz, with a nearly constant gain KVCO=4.16KHz/mV. Maximum output amplitude is 374mVpp @1.12MHz. THD is -41dB @321mVpp. Maximum average consumption is 355μW.

On designing OTA-C graphic-equalizers with MOSFET-triode transconductors

A CMOS audio-equalizer based on a parallel-array of 2nd-order bandpass-sections is presented and realized with triode transconductors. It has a programmable 12db-boost/cut on each of its three decade-bands, easily achieved through the linear dependence of gm on VDS. In accordance with a 0.8μm n-well double-metal fabrication process, a range of simulations supports theoretical analysis and circuit performance at different boost/cut scenarios. For VDD=3.3V, fullboosting stand-by prover consumption is 1.05mW. THD=-42.61dB@1Vpp and may be improved by balanced structures. Thermal- and I/f-noise spectral densities are 3.2μV/Hz12 and 18.2μV/Hz12@20Hz, respectively, for a dynamic range of 52.3dB@1Vpp. The equalizer effective area is 2.4mm2. The drawback of the existing transmission-zero due to the feedthrough-capacitance of a triode input-device is also addressed. The proposed topology can be extended to the design of more complex graphic-equalizers and hearing-aids.

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

On optimizing micropower MOS regulated cascode circuits on switched current techniques

Trade-off between settling time and micropower consumption in MOS regulated cascode current sources as building parts in high-accuracy, current-switching D/A converters is analyzed. The regulation-loop frequency characteristic is obtained and difficulties to impose a dominant-pole condition to the resulting 2nd-order system are discussed. Raising pole frequencies while meeting consumption requirements is basically limited by parasitic capacitances. An alternative is found by imposing a twin-pole system in which design constraints are somewhat relaxed and settling slightly faster. Relationships between pole frequencies, transistor geometry and bias are established. Simulated waveforms obtained with PSpice of designed circuits following a voltage perturbation suggest a good agreement with theory. The proposed approach applied to the design of a micropower current-mode D/A converter improves its simulated settling performance.

A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.

Topics in MOSFET network design /

Thesis--University of Illinois at Urbana-Champaign.

A database ATP simulated waveforms of shunt reactor switching cases with vacuum breakers on motor circuits

This paper presents a database ATP (Alternative Transient Program) simulated waveforms for shunt reactor switching cases with vacuum breakers in motor circuits following interruption of the starting current. The targeted objective is to provide multiple reignition simulated data for diagnostic and prognostic algorithms development, but also to help ATP users with practical study cases and component data compilation for shunt reactor switching. This method can be easily applied with different data for the different dielectric curves of circuit-breakers and networks. This paper presents design details, discusses some of the available cases and the advantages of such simulated data.

Rethinking genre studies through distribution analysis : issues in international horror movie circuits

The existence of any film genre depends on the effective operation of distribution networks. Contingencies of distribution play an important role in determining the content of individual texts and the characteristics of film genres; they enable new genres to emerge at the same time as they impose limits on generic change. This article sets out an alternative way of doing genre studies, based on an analysis of distributive circuits rather than film texts or generic categories. Our objective is to provide a conceptual framework that can account for the multiple ways in which distribution networks leave their traces on film texts and audience expectations, with specific reference to international horror networks, and to offer some preliminary suggestions as to how distribution analysis can be integrated into existing genre studies methodologies.