A low-voltage low-sensitivity sinusoidal VCO for DPLL realizations


Autoria(s): De Lima, Jader A.; Agostinho, Peterson R.
Contribuinte(s)

Universidade Estadual Paulista (UNESP)

Data(s)

27/05/2014

27/05/2014

07/09/2004

Resumo

A quasi-sinusoidal linearly tunable OTA-C VCO built with triode-region transconductors is presented. Oscillation upon power-on is ensured by RHP poles associated with gate-drain capacitances of OTA input devices. Since the OTA nonlinearity stabilizes the amplitude, the oscillation frequency f0 is first-order independent of VDD, making the VCO adequate to mixed-mode designs. A range of simulations attests the theoretical analysis. As part of a DPLL, the VCO was prototyped on a 0.8μm CMOS process, occupying an area of 0.15mm2. Nominal f0 is 1MHz, with K VCo=8.4KHz/mV. Measured sensitivity to VDD is below 2.17, while phase noise is -86dBc at 100-KHz offset. The feasibility of the VCO for higher frequencies is verified by a redesign based on a 0.35μm CMOS process and VDD=3.3V, with a linear frequency-span of l3.2MHz - 61.5MHz.

Identificador

http://dx.doi.org/10.1109/ISCAS.2004.1328313

Proceedings - IEEE International Symposium on Circuits and Systems, v. 1.

0271-4310

http://hdl.handle.net/11449/67875

10.1109/ISCAS.2004.1328313

WOS:000223122300198

2-s2.0-4344578485

Idioma(s)

eng

Relação

Proceedings - IEEE International Symposium on Circuits and Systems

Direitos

closedAccess

Palavras-Chave #Capacitance #CMOS integrated circuits #Computer simulation #Electric conductance #Electric potential #Jitter #Logic design #MOSFET devices #Switching #Transconductance #Transfer functions #OTA #Phase noise #Ring oscillators #Waveforms #Variable frequency oscillators
Tipo

info:eu-repo/semantics/conferencePaper