A new single-phase frequency adaptive Phase-Locked Loop (PLL) for harmonic measurement

The paper presents an improved Phase-Locked Loop (PLL) for measuring the fundamental frequency and selective harmonic content of a distorted signal. This information can be used by grid interfaced devices and harmonic compensators. The single-phase structure is based on the Synchronous Reference Frame (SRF) PLL. The proposed PLL needs only a limited number of harmonic stages by incorporating Moving Average Filters (MAF) for eliminating the undesired harmonic content at each stage. The frequency dependency of MAF in effective filtering of undesired harmonics is also dealt with by a proposed method for adaptation to frequency variations of input signal. The method is suitable for high sampling rates and a wide frequency measurement range. Furthermore, an extended model of this structure is proposed which includes the response to both the frequency and phase angle variations. The proposed algorithm is simulated and verified using Hardware-in-the-Loop (HIL) testing.

A phase-locked-loop design for the smooth operation of a hybrid microgrid

A microgrid contains both distributed generators (DGs) and loads and can be viewed by a controllable load by utilities. The DGs can be either inertial synchronous generators or non-inertial converter interfaced. Moreover, some of them can come online or go offline in plug and play fashion. The combination of these various types of operation makes the microgrid control a challenging task, especially when the microgrid operates in an autonomous mode. In this paper, a new phase locked loop (PLL) algorithm is proposed for smooth synchronization of plug and play DGs. A frequency droop for power sharing is used and a pseudo inertia has been introduced to non-inertial DGs in order to match their response with inertial DGs. The proposed strategy is validated through PSCAD simulation studies.

A frequency adaptive single-phase Phase-Locked Loop with harmonic rejection

An improved Phase-Locked Loop (PLL) for extracting phase and frequency of the fundamental component of a highly distorted grid voltage is presented. The structure of the single-phase PLL is based on the Synchronous Reference Frame (SRF) PLL and uses an All Pass Filter (APF) to generate the quadrature component from the single phase input voltage. In order to filter the harmonic content, a Moving Average Filter (MAF) is used, and performance is improved by designing a lead compensator and also a feed-forward compensator. The simulation results are compared to show the improved performance with feed-forward. In addition, the frequency dependency of MAF is dealt with by a proposed method for adaption to the frequency. This method changes the window size based on the frequency on a sample-by-sample basis. By using this method, the speed of resizing can be reduced in order to decrease the output ripples caused by window size variations.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Phase-Locked Loop design applied to frequency-modulated atomic force microscope

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

Discrete phase-locked loop systems and spreadsheets

This paper demonstrates the use of a spreadsheet in exploring non-linear difference equations that describe digital control systems used in radio engineering, communication and computer architecture. These systems, being the focus of intensive studies of mathematicians and engineers over the last 40 years, may exhibit extremely complicated behaviour interpreted in contemporary terms as transition from global asymptotic stability to chaos through period-doubling bifurcations. The authors argue that embedding advanced mathematical ideas in the technological tool enables one to introduce fundamentals of discrete control systems in tertiary curricula without learners having to deal with complex machinery that rigorous mathematical methods of investigation require. In particular, in the appropriately designed spreadsheet environment, one can effectively visualize a qualitative difference in the behviour of systems with different types of non-linear characteristic.

Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop

In this paper, two new dual-path based area efficient loop filtercircuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 CSM analog process with 1.8V supply. The proposed circuits achievedup to 85% savings in capacitor area. Simulations showed goodmatch of the new circuits with the conventional circuit. Theproposed circuits are particularly useful in applications thatdemand low die area.

SiGe V Band Wide Tuning-Range VCO and Frequency Divider for Phase Locked Loop

A V-band wide tuning-range VCO and high frequency divide-by-8 frequency divider using Infineon 0.35 µm SiGe HBT process are presented in this paper. An LC impedance peaking technique is introduced in the Miller divider to increase the sensitivity and operation frequency range of the frequency divider. Two static frequency dividers implemented using current mode logic are used to realize dividing by 4 in the circuit. The wide tuning range VCO operates from 51.9 to 64.1 GHz i.e. 20.3% frequency tuning range. The measured phase noise at the frequency divider output stage is around -98.5 dBc at 1 MHz. The circuit consumes 200mW and operates from a 3.5Vdc supply, and occupies 0.6×0.8 mm2 die area.

Phase-Locked loops lock-in range in Frequency Modulated-Atomic Force Microscope nonlinear control system

Since the mid 1980s the Atomic Force Microscope is one the most powerful tools to perform surface investigation, and since 1995 Non-Contact AFM achieved true atomic resolution. The Frequency-Modulated Atomic Force Microscope (FM-AFM) operates in the dynamic mode, which means that the control system of the FM-AFM must force the micro-cantilever to oscillate with constant amplitude and frequency. However, tip-sample interaction forces cause modulations in the microcantilever motion. A Phase-Locked loop (PLL) is used to demodulate the tip-sample interaction forces from the microcantilever motion. The demodulated signal is used as the feedback signal to the control system, and to generate both topographic and dissipation images. As a consequence, a proper design of the PLL is vital to the FM-AFM performance. In this work, using bifurcation analysis, the lock-in range of the PLL is determined as a function of the frequency shift (Q) of the microcantilever and of the other design parameters, providing a technique to properly design the PLL in the FM-AFM system. (C) 2011 Elsevier B.V. All rights reserved.

Phase-Locked loops lock-in range in Frequency Modulated-Atomic Force Microscope nonlinear control system

Since the mid 1980s the Atomic Force Microscope is one the most powerful tools to perform surface investigation, and since 1995 Non-Contact AFM achieved true atomic resolution. The Frequency-Modulated Atomic Force Microscope (FM-AFM) operates in the dynamic mode, which means that the control system of the FM-AFM must force the micro-cantilever to oscillate with constant amplitude and frequency. However, tip-sample interaction forces cause modulations in the microcantilever motion. A Phase-Locked loop (PLL) is used to demodulate the tip-sample interaction forces from the microcantilever motion. The demodulated signal is used as the feedback signal to the control system, and to generate both topographic and dissipation images. As a consequence, a proper design of the PLL is vital to the FM-AFM performance. In this work, using bifurcation analysis, the lock-in range of the PLL is determined as a function of the frequency shift (Q) of the microcantilever and of the other design parameters, providing a technique to properly design the PLL in the FM-AFM system. (C) 2011 Elsevier B.V. All rights reserved.