Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Tungsten Silicide Contacts to Polycrystalline Silicon and Silicon-Germanium Alloys

Novel CVD WSi2 technology with low series and contact resistance in SiGe HBTs was achieved. Specific contact resistance to Si1-xGex with 0

Giant piezoresistance in silicon-germanium alloys

We use first-principles electronic structure methods to show that the piezoresistive strain gauge factor of single-crystalline bulk n-type silicon-germanium alloys at carefully controlled composition can reach values of G = 500, three times larger than that of silicon, the most sensitive such material used in industry today. At cryogenic temperatures of 4 K we find gauge factors of G = 135 000, 13 times larger than that observed in Si whiskers. The improved piezoresistance is achieved by tuning the scattering of carriers between different (Delta and L) conduction band valleys by controlling the alloy composition and strain configuration.

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Paths Towards High Efficiency Silicon Photovoltaics

While photovoltaics hold much promise as a sustainable electricity source, continued cost reduction is necessary to continue the current growth in deployment. A promising path to continuing to reduce total system cost is by increasing device efficiency. This thesis explores several silicon-based photovoltaic technologies with the potential to reach high power conversion efficiencies. Silicon microwire arrays, formed by joining millions of micron diameter wires together, were developed as a low cost, low efficiency solar technology. The feasibility of transitioning this to a high efficiency technology was explored. In order to achieve high efficiency, high quality silicon material must be used. Lifetimes and diffusion lengths in these wires were measured and the action of various surface passivation treatments studied. While long lifetimes were not achieved, strong inversion at the silicon / hydrofluoric acid interface was measured, which is important for understanding a common measurement used in solar materials characterization.

Cryogenic deep reactive ion etching was then explored as a method for fabricating high quality wires and improved lifetimes were measured. As another way to reach high efficiency, growth of silicon-germanium alloy wires was explored as a substrate for a III-V on Si tandem device. Patterned arrays of wires with up to 12% germanium incorporation were grown. This alloy is more closely lattice matched to GaP than silicon and allows for improvements in III-V integration on silicon.

Heterojunctions of silicon are another promising path towards achieving high efficiency devices. The GaP/Si heterointerface and properties of GaP grown on silicon were studied. Additionally, a substrate removal process was developed which allows the formation of high quality free standing GaP films and has wide applications in the field of optics.

Finally, the effect of defects at the interface of the amorphous silicon heterojuction cell was studied. Excellent voltages, and thus efficiencies, are achievable with this system, but the voltage is very sensitive to growth conditions. We directly measured lateral transport lengths at the heterointerface on the order of tens to hundreds of microns, which allows carriers to travel towards any defects that are present and recombine. This measurement adds to the understanding of these types of high efficiency devices and may aid in future device design.

Brittle-ductile transition during diamond turning of single crystal silicon carbide

In this experimental study, diamond turning of single crystal 6H-SiC was performed at a cutting speed of 1 m/s on an ultra-precision diamond turning machine (Moore Nanotech 350 UPL) to elucidate the microscopic origin of ductile-regime machining. Distilled water (pH value 7) was used as a preferred coolant during the course of machining in order to improve the tribological performance. A high magnification scanning electron microscope (SEM FIB- FEI Quanta 3D FEG) was used to examine the cutting tool before and after the machining. A surface finish of Ra=9.2 nm, better than any previously reported value on SiC was obtained. Also, tremendously high cutting resistance was offered by SiC resulting in the observation of significant wear marks on the cutting tool just after 1 km of cutting length. It was found out through a DXR Raman microscope that similar to other classical brittle materials (silicon, germanium, etc.) an occurrence of brittle-ductile transition is responsible for the ductile-regime machining of 6H-SiC. It has also been demonstrated that the structural phase transformations associated with the diamond turning of brittle materials which are normally considered as a prerequisite to ductile-regime machining, may not be observed during ductile-regime machining of polycrystalline materials.

Ordering of Ge islands on Si(001) substrates patterned by nanoindentation

Spatial organization of Ge islands, grown by physical vapor deposition, on prepatterned Si(001) substrates has been investigated. The substrates were patterned prior to Ge deposition by nanoindentation. Characterization of Ge dots is performed by atomic force microscopy and scanning electron microscopy. The nanoindents act as trapping sites, allowing ripening of Ge islands at those locations during subsequent deposition and diffusion of Ge on the surface. The results show that island ordering is intrinsically linked to the nucleation and growth at indented sites and it strongly depends on pattern parameters.

Role of thermal annealing on SiGe thin films fabricated by PECVD

Amorphous Silicon Germanium (a-SiGe) thin films of 500 nm thickness are deposited on silicon substrates using Plasma Enhanced Chemical Vapour Deposition (PECVD). To obtain polycrystalline nature of films, thermal annealing is done at various temperature (450-600 degrees C) and time (1-10 h). The surface morphology of the pre- and post-annealed films is investigated using scanning electron microscopy (SEM) and atomic force microscopy (AFM). The crystallographic structure of the film is obtained by X-ray diffraction method. Raman spectroscopy is carried out to quantify the Ge concentration and the degree of strain relaxation in the film. Nano-indentation is performed to obtain the mechanical properties of the film. It is found that annealing reduces the surface roughness of the film and increases the Ge concentration in the film. The grain size of the film increases with increase in annealing temperature. The grain size is found to decrease with increase in annealing time up to 5 h and then increased. The results show that 550 degrees C for 5 h is the critical annealing condition for variation of structural and mechanical properties of the film. Recrystallization starts at this condition and results in finer grains. An increase in hardness value of 7-8 GPa has been observed. Grain growth occurs above this critical annealing condition and degrades the mechanical properties of the film. The strain in the film is only relaxed to about 55% even for 10 h of annealing at 600 degrees C. Transmission Electron Microscopy (TEM) observations show that the strain relaxation occurs by forming misfit dislocations and these dislocations are confined to the SiGe/Si interface. (C) 2015 Elsevier Ltd. All rights reserved.

Strain-induced anodization of SiGe/Si multiple layers to form high density SiGe/Si heterogeneous nanorods

Nation Natural Science Foundation of China 50672079 60676027 60837001 60776007; National Basic Research Program of China (973 Program) 2007CB613404; China-MOST International Sci & Tech Cooperation and Exchange 2008DFA51230

Comparative study of the structural properties of nanocrystalline Ge : H plasma deposited onto the cathode and the anode using high hydrogen dilutions

Nanocrystalline Ge:H thin films were deposited simultaneously on both electrodes of a conventional capacitively coupled reactor for plasma enhanced chemical vapor deposition using highly H-2 diluted GeH4 as the source gas. The structure of the films was investigated by Raman scattering and X-ray diffraction as a function of substrate temperature, H-2 dilution, and r.f. power. The hydrogen concentrations and bonding configurations were determined by infrared absorption spectroscopy. For anodic deposition, the preferred crystallographic orientation and film crystallinity depend rather strongly on the deposition parameters. This dependence can be explained by changing surface mobilities of adsorbed precursors due to changes in the hydrogen coverage of the growing surface. Cathodic deposition is much less sensitive to variations in the deposition parameters. It generally results in films of high crystallinity with randomly oriented crystallizes. Some possible mechanisms for these differences between anodic and cathodic deposition are discussed. (C) 1999 Elsevier Science S.A. All rights reserved.

Strain relaxation of GeSi alloy with low dislocation density grown on low-temperature Si buffers

We have developed a low-temperature (LT) growth technique. Even with Ge fraction x upto 90%, the total thickness of fully relaxed GexSi1-x buffers can he reduced to 1.7 mu m with dislocation density lower than 5 x 10(6) cm(-2). The surface roughness is no more than 6 nm. The strain relaxation is quite inhomogeneous From the beginning. Stacking faults generate and form the mismatch dislocations in the interface of GeSi/LT-Si. (C) 1999 Elsevier Science B.V. All rights reserved.

CHARACTERISTICS OF OXIDES FORMED FROM A SI0.5GE0.5

X-ray photoelectron spectroscopy (XPS) combined with Auger electron spectroscopy (AES) have been used to study the oxides from a Si0.5Ge0.5 alloy grown by molecular beam epitaxy (MBE). The oxidation was performed at 1000 degrees C wet atmosphere. The oxide consists of two layers: a mixed (Si,Ge)O-x layer near the surface and a pure SiOx layer underneath. Ge is rejected from the pure SiOx and piles up at the SiOx/SiGe interface. XPS analysis demonstrates that the chemical shifts of Si 2p and Ge 3d in the oxidized Si0.5Ge0.5 are significantly larger than those in SiO2 and GeO2 formed from pure Si and Ge crystals.