Effects of techniques of implanting nitrogen into buried oxide on the characteristics of partially depleted SOIPMOSFET

Effects of techniques of implanting nitrogen into buried oxide on the characteristics of the partially depleted silicon-on-insulator (SOI) p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) have been studied with three different nitrogen implantation doses, 8 x 10(15), 2 x 10(16), and 1 x 10(17) cm(-2). The experimental results show that this technology can affect the threshold voltage, channel hole mobility and output characteristics of the partially depleted SOI PMOSFETs fabricated with the given material and process. For each type of the partially depleted SOI PMOSFET with nitrided buried oxide, the absolute value of the average threshold voltage increases due to the nitrogen implantation. At the same time, the average channel hole mobility decreases because of the nitrogen implantation. In particular, with the high nitrogen implantation doses, the output characteristic curves of the tested transistors present a distinct kink effect, which normally exists in the characteristic output curves of only partially depleted SOI NMOSFETs.

Effect of the technology of implanting nitrogen into buried oxide on the radiation hardness of the top gate oxide for partially depleted SOIPMOSFET

The effect of implanting nitrogen into buried oxide on the top gate oxide hardness against total irradiation does has been investigated with three nitrogen implantation doses (8 x 10(15), 2 x 10(16) and 1 x 10(17) cm(-2)) for partially depleted SOI PMOSFET. The experimental results reveal the trend of negative shift of the threshold voltages of the studied transistors with the increase of nitrogen implantation dose before irradiation. After the irradiation with a total dose of 5 x 10(5) rad(Si) under a positive gate voltage of 2V, the threshold voltage shift of the transistors corresponding to the nitrogen implantation dose 8 x 10(15) cm(-2) is smaller than that of the transistors without implantation. However, when the implantation dose reaches 2 x 10(16) and 1 x 10(17) cm(-2), for the majority of the tested transistors, their top gate oxide was badly damaged due to irradiation. In addition, the radiation also causes damage to the body-drain junctions of the transistors with the gate oxide damaged. All the results can be interpreted by tracing back to the nitrogen implantation damage to the crystal lattices in the top silicon.

Effects of the technology of implanting nitrogen into buried oxide layer on the characteristics of partially depleted SOI nMOSFET

The effects, caused by the process of the implantation of nitrogen in the buried oxide layer of SIMOX wafer, on the characteristics of partially depleted silicon-on-insulator nMOSFET have been studied. The experimental results show that the channel electron mobilities of the devices fabricated on the SIMON (separation by implanted oxygen and nitrogen) wafers are lower than those of the devices made on the SIMOX (separation by implanted oxygen) wafers. The devices corresponding to the lowest implantation dose have the lowest mobility within the range of the implantation dose given in this paper. The value of the channel electron mobility rises slightly and tends to a limit when the implantation dose becomes greater. This is explained in terms of the rough Si/SiO2 interface due to the process of implantation of nitrogen. The increasing negative shifts of the threshold voltages for the devices fabricated on the SIMON wafers are also observed with the increase of implanting dose of nitrogen. However, for the devices fabricated on the SIMON wafers with the lowest dose of implanted nitrogen in this paper, their threshold voltages are slightly larger on the average than those prepared on the SIMOX wafers. The shifts are considered to be due to the increment of the fixed oxide charge in SiO2 layer and the change of the density of the interface-trapped charge with the value and distribution included. In particular, the devices fabricated on the SIMON wafers show a weakened kink effect, compared to the ones made on the SIMOX wafers.

Effect of implantation of nitrogen into SIMOX buried oxide on its fixed positive charge density

In order to obtain greater radiation hardness for SIMOX (separation by implanted oxygen) materials, nitrogen was implanted into SIMOX BOX (buried oxide). However, it has been found by the C-V technique employed in this work that there is an obvious increase of the fixed positive charge density in the nitrogen-implanted BOX with a 150 out thickness and 4 x 10(15) cm(-2) nitrogen implantation dose, compared with that unimplanted with nitrogen. On the other hand, for the BOX layers with a 375 nm thickness and implanted with 2 x 10(15) and 3 x 10(15) cm(-2) nitrogen doses respectively, the increase of the fixed positive charge density induced by implanted nitrogen has not been observed. The post-implantation annealing conditions are identical for all the nitrogen-implanted samples. The increase in fixed positive charge density in the nitrogen-implanted 150 nm BOX is ascribed to the accumulation of implanted nitrogen near the BOX/Si interface due to the post-implantation annealing process according to SIMS results. In addition, it has also been found that the fixed positive charge density in initial BOX is very small. This means SIMOX BOX has a much lower oxide charge density than thermal SiO2 which contains a lot of oxide charges in most cases.

Influence of nitrogen implantation into the buried oxide on the radiation hardness of silicon-on-insulator wafers

摘要: In order to improve the total-dose radiation hardness of the buried oxide of separation by implanted oxygen silicon-on-insulator wafers, nitrogen ions were implanted into the buried oxide with a dose of 10(16)cm(-2), and subsequent annealing was performed at 1100 degrees C. The effect of annealing time on the radiation hardness of the nitrogen implanted wafers has been studied by the high frequency capacitance-voltage technique. The results suggest that the improvement of the radiation hardness of the wafers can be achieved through a shorter time annealing after nitrogen implantation. The nitrogen-implanted sample with the shortest annealing time 0.5 h shows the highest tolerance to total-dose radiation. In particular, for the 1.0 and 1.5 h annealing samples, both total dose responses were unusual. After 300-krad(Si) irradiation, both the shifts of capacitance-voltage curve reached a maximum, respectively, and then decreased with increasing total dose. In addition, the wafers were analysed by the Fourier transform infrared spectroscopy technique, and some useful results have been obtained.

Sensitivity of Total-Dose Radiation Hardness of SIMOX Buried Oxides to Doses of Nitrogen Implantation into Buried Oxides

In order to improve the total-dose radiation hardness of the buried oxides(BOX) in the structure of separa tion-by-implanted-oxygen(SIMOX) silicon-on-insulator(SOI), nitrogen ions are implanted into the buried oxides with two different doses,2 × 1015 and 3 × 1015 cm-2 , respectively. The experimental results show that the radiation hardness of the buried oxides is very sensitive to the doses of nitrogen implantation for a lower dose of irradiation with a Co-60 source. Despite the small difference between the doses of nitrogen implantation, the nitrogen-implanted 2 × 1015 cm-2 BOX has a much higher hardness than the control sample (i. e. the buried oxide without receiving nitrogen implantation) for a total-dose irradiation of 5 × 104rad(Si), whereas the nitrogen-implanted 3 × 1015 cm-2 BOX has a lower hardness than the control sample. However,this sensitivity of radiation hardness to the doses of nitrogen implantation reduces with the increasing total-dose of irradiation (from 5 × 104 to 5 × 105 rad (Si)). The radiation hardness of BOX is characterized by MOS high-frequency (HF) capacitance-voltage (C-V) technique after the top silicon layers are removed. In addition, the abnormal HF C-V curve of the metal-silicon-BOX-silicon(MSOS) structure is observed and explained.

Improved Thermal Performance of SOI Using Compound Buried Layer

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of SiO2, polycrystalline silicon (polysilicon), and SiO2. The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than SiO2. CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard SiO2 buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0-μm SiO2 BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 μm manufactured on CBL SOI substrates showed a 5%-17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI.

Process control of cantilever deflection for sensor application based on optical waveguides

This paper reports on the fabrication of cantilever silicon-on-insulator (SOI) optical waveguides and presents solutions to the challenges of using a very thin 260-nm active silicon layer in the SOI structure to enable single-transverse-mode operation of the waveguide with minimal optical transmission losses. In particular, to ameliorate the anchor effect caused by the mean stress difference between the active silicon layer and buried oxide layer, a cantilever flattening process based on Ar plasma treatment is developed and presented. Vertical deflections of 0.5 mu m for 70-mu m-long cantilevers are mitigated to within few nanometers. Experimental investigations of cantilever mechanical resonance characteristics confirm the absence of significant detrimental side effects. Optical and mechanical modeling is extensively used to supplement experimental observations. This approach can satisfy the requirements for on-chip simultaneous readout of many integrated cantilever sensors in which the displacement or resonant frequency changes induced by analyte absorption are measured using an optical-waveguide-based division multiplexed system.

Influence of lattice temperature on SOI MOSFET's output characteristics

An explanation for the observed variations in the output behaviour of SOI transistors with different buried oxide thicknesses is presented. At low drain bias, the temperature effects are relatively insignificant while at high drain bias, the temperature effects dominate the nonlinear behaviour of the output characteristics.

Switching speed enhancement of the LDMOSFETs using partial-SOI technology

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Analysis on the off-state design and characterization of LIGBTs in partial SOI technology

Classical high voltage devices fabricated on SOI substrates suffer from a backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes the off-state behavior of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrate. During the initial development stage the SJ LIGBT was found to have very high leakage. This was attributed to the back and side coupling effects. This paper discusses these effects and shows how this problem could be successfully addressed with minimal modifications of device layout. The off-state performance of the SJ LIGBT at different temperatures is assessed and a comparison to an equivalent LDMOSFET is given. © 2014 Elsevier Ltd. All rights reserved.

Study of GaN growth on ultra-thin Si membranes

10 mu m-thick ultra-thin Si (111) membranes for GaN epi-layers growth were successfully fabricated on silicon-on-insulator (SOI) substrate by backside etching the handle Si and buried oxide (BOX) layer. Then 1 mu m-thick GaN layers were deposited on these Si membranes by metal-organic chemical vapor deposition (MOCVD). The crack-free areas of 250 mu m, x 250 mu m were obtained on the GaN layers due to the reduction of thermal stress by using these ultra-thin Si membranes, which was further confirmed by the photoluminescence (PL) spectra and the simulation results from the finite element method calculation by using the software of ANSYS. In this paper, a newly developed approach was demonstrated to utilize micromechanical structures for GaN growth, which would improve the material quality of the epi-layers and facilitate GaN-based micro electro-mechanical system (MEMS) fabrication, especially the pressure sensor, in the future applications. (C) 2008 Elsevier Ltd. All rights reserved.