969 resultados para Integrated circuit interconnections


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Using thermal evaporation, Ti/6H-SiC Schottky barrier diodes (SBD) were fabricated. They showed good rectification characteristics from room temperature to 200degreesC. At low current density. the current conduction mechanism follows the thermionic emission theory. These diodes demonstrated a low reverse leakage current of below 1 X 10(-4)Acm(-2). Using neon implantation to form the edge termination, the breakdown voltage was improved to be 800V. In addition. these SBDs showed superior switching characteristics.

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The semiconductor microlasers with an equilateral triangle resonator which can be fabricated by dry etching technique from the laser wafer of the edge emitting laser, are analyzed by FDTD technique and rate equations. The results show that ETR microlaser is suitable to realize single mode operation. By connecting an output waveguide to one of the vertices of the ETR, we still can get the confined modes with high quality factors. The EM microlasers are potential light sources for photonic integrated circuits.

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We report some investigations on vertical cavity surface emitting laser (VCSEL) arrays and VCSEL based optoelectronic smart photonic multiple chip modules (MCM), consisting of 1x16 vertical cavity surface emitting laser array and 16-channel lasers driver 0.35 Pin CMOS circuit. The hybrid integrated multiple chip modules based on VCSEL operate at more than 2GHz in -3dB frequency bandwidth.

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Deep level transient spectroscopy (DLTS) technique was used to investigate deep electron states in n-type Al-doped ZnS1-xTex epilayers grown by molecular fiction epitaxy (MBE), Deep level transient Fourier spectroscopy (DLTFS) spectra of the Al-doped ZnS1-xTex (x = 0. 0.017, 0.04 and 0.046. respectively) epilayers reveal that At doping leads to the formation of two electron traps at 0.21 and 0.39 eV below the conduction hand. 1)DLTFS results suggest that in addition to the rules of Te as a component of [lie alloy as well as isoelectronic centers, Te is also involved in the formation of all electron trip, whose energy level relative to the conduction hand decreases a, Te composition increases.

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A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.

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CMOS/SOS devices have lower carriers mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly results from the defects of heteroepitaxial silicon film, especially from the defects near Si-Sapphire interface. This paper describes the experiment results of CMOS/SOS devices characteristics improved by a better epitaxial silicon quality which is obtained by a modified solid phase epitaxy.

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In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H2SO4/H2O2 (SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.

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In this paper a new half-flash architecture for high speed video ADC is presented. Based on a high speed single-way analog switch circuit, this architecture effectively reduces the number of elements. At the same lime no sacrifice of speed is needed compared with the normal half-flash structure.

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In this paper we introduce a new Half-flash analog switch ADC architecture. And we discuss two methods to design the values of the cascaded resistors which generate the reference voltages. Derailed analysis about the effect of analog switches and comparators on reference voltages, and the methods to set the resistor values and correspond;ng voltage errors are given.

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This paper introduces a new highspeed single-way analog switch which has both highspeed high-resolution mono-direction analog transmission gate function and high-speed digital logic gate function with normal bipolar technology. The analysis of static and transient switching performances as an analog transmission gate is emphasized in the paper. In order to reduce the plug-in effect on high-speed high-resolution systems, an optimum design scheme is also given. This scheme is to achieve accelerated dynamic response with very low bias power dissipation. The analysis of PSPICE simulation as well as the circuit test results confirms the feasibility of the scheme. Now, the circuit has been applied effectively to the designs of novel highspeed A/D and D/A converters.

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In this paper, a one-way NMOS analog switch featuring a low plug-in consumption is presented. The performances of analog switch, especially the performances of source follower are simulated under different conditions with PSPICE. Simulation results and factors affecting the deviation between input and output are analyzed, some advice on how to reduce the deviation between input and output is given. Ar the end of the paper, voltage relationship between input and output of the analog switch is obtained. Function of first degree, Vout = kVin + V0, is used to approximate the voltage relationship. The simulation results anti the value achieved from the approximation equation are given as well.

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Self-organized InAs quantum; dots sheets are grown on GaAs(100) substrate and tapped by 80nm GaAs layer with molecular beam epitaxy. Samples were annealed and characterized with Raman spectra, transmission electron microscopy (TEM) and photolumincscence (PL). The Raman spectra indicates arsenic clusters in the GaAs capping layer. The TEM analysis revealed the relaxation of strain in some InAs islands with the introduction of the network of 90 dislocations. In addition, the structural changes also lead to the changes of the PL spectra from me InAs islands. Their correlation was discussed, Our results suggest:est that annealing may be used to intentionally modify me properties of self-organized InAs islands on GaAs.

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This paper presents a detailed PL study of Fe2+ related four zero-phonon(ZP) lines and their related phonon sidebands. Four zero-phonon transitions at approximate to 2800 cm(-1) along with the accompanying phonon sidebands extending down to 2400 cm(-1). There are ta two prominent regions in the phonon sidebands. One is ascribed to coupling to acoustic-type phonons (2700 cm(-1) region), the other is due to coupling to optic-type phonons (2500 cm(-1) region). Beside broad coupling with lattice modes, there are several groups of lines. They are ascribed to resonant modes, impurities induced gap modes and local modes.

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Quantum dot lasers are predicted to have proved lasing characteristics compared to quantum well and quantum wire lasers. We report on quantum dot lasers with active media of vertically stacked InAs quantum dots layers grown by molecular beam epitaxy. The laser diodes were fabricated and the threshold current density of 220 A/cm(2) was achieved at room temperature with lasing wavelength of 951 nm. The characteristic temperature To was measured to be 333K and 157K for the temperature range of 40-180K and 180-300K, respectively.