Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

The effects of key geometrical parameters on the performance of integrated spiral inductors are investigated with the 3D electromagnetic simulator HFSS. While varying geometrical parameters such as the number of turns （N）,the width of the metal traces （W）,the spacing between the traces （S）,and the inner diameter （ID）, changes in the performance of the inductors are analyzed in detail. The reasons for these changes in performance are presented. Simulation results indicate that the performance of an integrated spiral inductor can be improved by optimizing its layout. Some design rules are summarized.

Fabrication of a Silicon-Based Microprobe for Neural Interface Applications

A two-dimensional (2D) multi-channel silicon-based microelectrode array is developed for recording neural signals. Three photolithographic masks are utilized in the fabrication process. SEM images show that the microprobe is 1. 2mm long,100μm wide,and 30μm thick, with recording sites spaced 200μm apart for good signal isolation. For the individual recording sites, the characteristics of impedance versus frequency are shown by in vitro testing. The impedance declines from 14MΩ to 1.9kv as the frequency changes from 0 to 10MHz. A compatible PCB (print circuit board) aids in the less troublesome implantation and stabilization of the microprobe.

Low-Microwave Loss Coplanar Waveguides Fabricated on High-Resistivity Silicon Substrate

Three kinds of coplanar waveguides （CPWs） are designed and fabricated on different silicon substrates---common low-resistivity silicon substrate （LRS）, LRS with a 3μm-thick silicon oxide interlayer, and high-resistivity silicon （HRS） substrate. The results show that the microwave loss of a CPW on LRS is too high to be used, but it can be greatly reduced by adding a thick interlayer of silicon oxide between the CPW transmission lines and the LRS.A CPW directly on HRS shows a loss lower than 2dB/cm in the range of 0-26GHz and the process is simple,so HRS is a more suitable CPW substrate.

Effect of Silicon-on-Insulator Substrate on Residual Strain in 3C-SiC Films

One group of SiC films are grown on silicon-on-insulator （SOI） substrates with a series of silicon-overlayer thickness. Raman scattering spectroscopy measurement clearly indicates that a systematic trend of residual stress reduction as the silicon over-layer thickness decreases for the SOI substrates. Strain relaxation in the SiC epilayer is explained by force balance approach and near coincidence lattice model.

Photoelectric Conversion Efficiency Enhanced by Tilting Monocrystalline Silicon Photovoltaic Device

Based on the idea of tilting a photoelectric conversion device,the monocrystalline silicon p-n junction device was tilted to make light incident upon the device at an angle of 45° with the normal of the device surface,resulting in infrared multiple-internal-reflection inside the device.The internal reflection leads to path length increase of infrared light,making the enhancement of infrared absorption of the device.An increase of 11% in energy conversion efficiency has been obtained through tilting the device.

Analysis and Simulation of S-shaped Waveguide in Silicon-on-insulator

The simulation and analysis of S-shaped waveguide bend are presented.Bend radius larger than 30 mm assures less than 0.5 dB radiation loss for a 4-μm-wide silicon-on-insulator waveguide bend with 2-μm etch depth.Intersection angle greater than 20° provides negligible crosstalk (＜-30 dB) and very low insertion loss.Any reduction in bend radius and intersection angle is at the cost of the degradation of characteristics of bent waveguide and intersecting waveguide, respectively.

Design and numerical analysis for low birefringence silica on silicon waveguides

A new fabrication technology for three-dimensionally buried silica on silicon optical waveguide based on deep etching and thermal oxidation is presented. Using this method, a silicon layer is left at the side of waveguide. The stress distribution and effective refractive index are calculated by using finite element method and finite different beam propagation method, respectively. The results indicate that the stress of silica on silicon optical waveguide fabricated by this method can be matched in parallel and vertical directions and stress birefringence can be effectively reduced due to the side-silicon layer.

Polarization-Insensitive Silica on Silicon Arrayed Waveguide Grating Design

A new technology for fabrication of silica on silicon arrayed waveguide grating (AWG) based on deep etching and thermal oxidation is presented.Using this method,a silicon layer is remained at the side of waveguide.The stress distribution and effective refractive index of waveguide fabricated by this approach are calculated using finite element and finite difference beam propagation method,respectively.The results of these studies indicate that the stress of silica on silicon optical waveguide can be matched in parallel and vertical direction and AWG polarization dependent wavelength (PDλ) can be reduced effectively due to side-silicon layer.

Design and Fabrication of Thermo-Optic 4×4 Switching Matrix in Silicon-on-Insulator

A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements，is designed and fabricated.The minimum and maximum excess loss for the matrix are 6.6 and 10.4dB,respectively.The crosstalk in the matrix is measured to be between －12 and －19.8dB.The switching speed of the matrix is less than 30μs.The power consumption for the single switch element is about 330mW.

High-speed electrooptical VOA integrated in silicon-on-insulator

In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) inte-grated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption toachieve attenuation. Beam propagation method (BPM) and two-dimensional semiconductor device simu-lation tool PISCES-Ⅱ were used to analyze the dc and transient characteristics of the device. The devicehas a response time (including rise time and fall time) less than 200 ns, much faster than the thermoopticand micro-electromechanical systems (MEMSs) based VOAs.

Integrated MMI Optical Couplers and Optical Switches in Silicon-on-Insulator Technology

Integrated multimode interference (MMI) coupler based on silicon-on-insulator(SOI) has been becoming a kind of more and more attractive device in optical systems. SiO2thin cladding layers (＜1.0 μm) can be usedin SOI waveguide due to the large index step be-tween Si and SiO2, making them compatible with VLSI technology. The design and fabrica-tion of MMI optical couplers and optical switches in SOI technology are presented in thepa-per. We demonstrated the switching time of 2 × 2 MMI-MZI thermo-optical switch is less than 20 μs:

Design and Fabrication of Ultracompact 3-dB MMI Coupler in Silicon-on-Insulator

An ultracompact 3-dB coupler is designed and fabricated in silicon-on-insulator,based on 12 line tapered multimode interference(MMI) coupler.Comparing with the conventional straigth MMI coupler,the device is-40% shorter in length.The device exhibits uniformity of 1.3dB and excess loss of 2.5dB

Fabrication of Silicon Condenser Microphone Using Oxidized Porous Silicon as Sacrificial Layer

A new technique to fabricate silicon condenser microphone is presented. The technique is based on the use of oxidized porous silicon as sacrificial layer for the air gap and the heavy p~+-doping silicon of approximately 15μm thickness for the stiff backplate. The measured sensitivity of the microphone fabricated with this technique is in the range from -45dB (5.6mV/Pa) to -55dB (1.78mV/Pa) under the frequency from 500Hz to 10kHz, and shows a gradual increase at high frequency. The cut-off frequency is above 20kHz.

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入

Crystal-Field Symmetry of Luminescence Center in Er-Implanted Silicon

于2010-11-23批量导入