Recent Progress in Silicon Electro-optic Modulators for High Speed Applications

Silicon-based high-speed electro-optical modulator is the key component of silicon photonics for future communiction and interconnection systems. In this paper, introduced are the optical mudulation mechanisms in silicon, reviewed are some recent progresses in high-speed silicon modulators, and analyzed are advantages and shortages of the silicon modulators of different types.

Heteroepitaxial Growth of 3C-SiC Films on Maskless Patterned Silicon Substrates

Heteroepitaxial growth of 3C-SiC on patterned Si substrates by low pressure chemical vapor deposition (LPCVD) has been investigated to improve the crystal quality of 3C-SiC films. Si substrates were patterned with parallel lines, 1 to 10μm wide and spaced 1 to 10μm apart, which was carried out by photolithography and reactive ion etching. Growth behavior on the patterned substrates was systematically studied by scanning electron microscopy (SEM). An air gap structure and a spherical shape were formed on the patterned Si substrates with different dimensions. The air gap formed after coalescence reduced the stress in the 3C-SiC films, solving the wafer warp and making it possible to grow thicker films. XRD patterns indicated that the films grown on the maskless patterned Si substrates were mainly composed of crystal planes with (111) orientation.

Fabrication of Silicon Crystal-Facet-Dependent Nanostructures by Electron-Beam Lithography

Silicon crystal-facet-dependent nanostructures have been successfully fabricated on a (100)-oriented silicon-on-insulator wafer using electron-beam lithography and the silicon anisotropic wet etching technique. This technique takes ad-vantage of the large difference in etching properties for different crystallographic planes in alkaline solution. The mini-mum size of the trapezoidal top for those Si nanostructures can be reduced to less than 10nm. Scanning electron microscopy(SEM) and atomic force microscopy (AFM) observations indicate that the etched nanostructures have controllable shapes and smooth surfaces.

An Improvement on 2× 2 Silicon-on-Insulator Mach-Zehnder Thermo-Optical Switch

An improved 2 ×2 silicon-on-insulator Mach-Zehnder thermo-optical switch is designed and fabricated, which is based on strongly guided multimode interference couplers and single- mode phase-shifting arms. The multimode interference couplers and input/output waveguides are deeply etched to improve coupler performances and coupler-waveguide coupling efficiencies. However, shallow etching is used in the phase-shifting arms to guarantee single-mode property. The strongly guided coupler presents an attractive uniformity about 0. 03 dB and a low propagation loss of -0.6 dB. The 2× 2 switch shows an insertion loss as low as -6.8 dB, where the fiber-waveguide coupling loss of -4.3 dB is included, and the response-time is measured as short as 6.8 μs, which are much better than our previous results.

A High-Performance Silicon Electro-Optic Phase Modulator with a Triple MOS Capacitor

We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor (MOS) capacitor configuration integrated into silicon-on-insulator (SOI).Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure,which boosts the modulation efficiency compared with a single MOS capacitor.The simulation results demonstrate that the VπLπ product is 2.4V·cm.The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve,respectively,indicating a bandwidth of 8GHz.The phase shift efficiency and bandwidth can be enhanced by rib width scaling.

360-nm Photoluminescence from Silicon Oxide Films Embedded with Silicon Nanocrystals

Si-rich silicon oxide films were deposited by RF magnetron sputtering onto composite Si/SiO2 targets. After annealed at different temperature, the silicon oxide films embedded with silicon nanocrystals were obtained. The photoluminescenee（PL） from the silicon oxide films embedded with silicon nanocrystals was observed at room temperature. The strong peak is at 360 nm, its position is independent of the annealing temperature. The origin of the 360-nm PL in the silicon oxide films embedded with silicon nanoerystals was discussed.

Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

The effects of key geometrical parameters on the performance of integrated spiral inductors are investigated with the 3D electromagnetic simulator HFSS. While varying geometrical parameters such as the number of turns （N）,the width of the metal traces （W）,the spacing between the traces （S）,and the inner diameter （ID）, changes in the performance of the inductors are analyzed in detail. The reasons for these changes in performance are presented. Simulation results indicate that the performance of an integrated spiral inductor can be improved by optimizing its layout. Some design rules are summarized.

Fabrication of a Silicon-Based Microprobe for Neural Interface Applications

A two-dimensional (2D) multi-channel silicon-based microelectrode array is developed for recording neural signals. Three photolithographic masks are utilized in the fabrication process. SEM images show that the microprobe is 1. 2mm long,100μm wide,and 30μm thick, with recording sites spaced 200μm apart for good signal isolation. For the individual recording sites, the characteristics of impedance versus frequency are shown by in vitro testing. The impedance declines from 14MΩ to 1.9kv as the frequency changes from 0 to 10MHz. A compatible PCB (print circuit board) aids in the less troublesome implantation and stabilization of the microprobe.

Low-Microwave Loss Coplanar Waveguides Fabricated on High-Resistivity Silicon Substrate

Three kinds of coplanar waveguides （CPWs） are designed and fabricated on different silicon substrates---common low-resistivity silicon substrate （LRS）, LRS with a 3μm-thick silicon oxide interlayer, and high-resistivity silicon （HRS） substrate. The results show that the microwave loss of a CPW on LRS is too high to be used, but it can be greatly reduced by adding a thick interlayer of silicon oxide between the CPW transmission lines and the LRS.A CPW directly on HRS shows a loss lower than 2dB/cm in the range of 0-26GHz and the process is simple,so HRS is a more suitable CPW substrate.

Effect of Silicon-on-Insulator Substrate on Residual Strain in 3C-SiC Films

One group of SiC films are grown on silicon-on-insulator （SOI） substrates with a series of silicon-overlayer thickness. Raman scattering spectroscopy measurement clearly indicates that a systematic trend of residual stress reduction as the silicon over-layer thickness decreases for the SOI substrates. Strain relaxation in the SiC epilayer is explained by force balance approach and near coincidence lattice model.

Photoelectric Conversion Efficiency Enhanced by Tilting Monocrystalline Silicon Photovoltaic Device

Based on the idea of tilting a photoelectric conversion device,the monocrystalline silicon p-n junction device was tilted to make light incident upon the device at an angle of 45° with the normal of the device surface,resulting in infrared multiple-internal-reflection inside the device.The internal reflection leads to path length increase of infrared light,making the enhancement of infrared absorption of the device.An increase of 11% in energy conversion efficiency has been obtained through tilting the device.

Analysis and Simulation of S-shaped Waveguide in Silicon-on-insulator

The simulation and analysis of S-shaped waveguide bend are presented.Bend radius larger than 30 mm assures less than 0.5 dB radiation loss for a 4-μm-wide silicon-on-insulator waveguide bend with 2-μm etch depth.Intersection angle greater than 20° provides negligible crosstalk (＜-30 dB) and very low insertion loss.Any reduction in bend radius and intersection angle is at the cost of the degradation of characteristics of bent waveguide and intersecting waveguide, respectively.

Design and numerical analysis for low birefringence silica on silicon waveguides

A new fabrication technology for three-dimensionally buried silica on silicon optical waveguide based on deep etching and thermal oxidation is presented. Using this method, a silicon layer is left at the side of waveguide. The stress distribution and effective refractive index are calculated by using finite element method and finite different beam propagation method, respectively. The results indicate that the stress of silica on silicon optical waveguide fabricated by this method can be matched in parallel and vertical directions and stress birefringence can be effectively reduced due to the side-silicon layer.

Polarization-Insensitive Silica on Silicon Arrayed Waveguide Grating Design

A new technology for fabrication of silica on silicon arrayed waveguide grating (AWG) based on deep etching and thermal oxidation is presented.Using this method,a silicon layer is remained at the side of waveguide.The stress distribution and effective refractive index of waveguide fabricated by this approach are calculated using finite element and finite difference beam propagation method,respectively.The results of these studies indicate that the stress of silica on silicon optical waveguide can be matched in parallel and vertical direction and AWG polarization dependent wavelength (PDλ) can be reduced effectively due to side-silicon layer.

Design and Fabrication of Thermo-Optic 4×4 Switching Matrix in Silicon-on-Insulator

A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements，is designed and fabricated.The minimum and maximum excess loss for the matrix are 6.6 and 10.4dB,respectively.The crosstalk in the matrix is measured to be between －12 and －19.8dB.The switching speed of the matrix is less than 30μs.The power consumption for the single switch element is about 330mW.