Crystallization and phase transformation behaviour of electroless nickel-phosphorus deposits with low and medium phosphorus contents under continuous heating

Electroless nickel-phosphorus deposits with 5-8 wt% P and 3-5 wt% P were analysed for the effects of continuous heating on the crystallization kinetics and phase transformation behaviour of the deposits. The as-deposited coatings consist of a mixture of amorphous and microcrystalline nickel phases, featuring in their X-ray diffraction patterns. Continuous heating processes to 300C-800C at 20C/min were carried out on the deposits in a differential scanning calorimetric apparatus. The subsequent X-ray diffraction analyses show that the sequence of phase transformation process was: amorphous phase + microcrystalline nickel, f.c.c. nickel + Ni3P stable phases. Preferred orientation of nickel {200} plane developed in the deposits after the heating processes. Differential scanning calorimetry of the deposits indicates that the crystallization temperatures increased with decreasing phosphorus content, and increasing heating rate. Crystallization activation energies of the deposits (230 and 322 kJ/mol, respectively) were calculated using the peak temperatures of crystallization process, from the differential scanning calorimetric curves at the heating rates ranging from 5 to 50C/min. It was found that the deposit with lower phosphorus content has higher activation energy.

Synchrotron X-ray diffraction study of the phase transformations in titanium alloys

High-resolution synchrotron X-ray diffraction was used to study the phase transformations in titanium alloys. Three titanium alloys were investigated: Ti-6Al-4V, Ti-6Al-2Sn-4Zr-2Mo-0.08Si and beta21s. Both room and high temperature measurements were performed. The room temperature experiments were performed to study the structure of the alloys after different heat treatments, namely as received (AR), furnace cooling (FC), water quenching (WQ) and water quenching followed by ageing. The alpha, alpha', alpha'' and beta phases were observed in different combinations depending on the heat treatment conditions and the alloy studied. A multicomponent hexagonal close packed (hcp) alpha phase, with different c and the same a lattice parameters, was detected in Ti-6Al-4V after FC. High temperature synchrotron X-ray diffraction was used for 'in situ' study of the transformations on the sample surface at elevated temperatures. The results were used to trace the kinetics of surface oxidation and the concurrent phase transformations taking place under different conditions. The influence of the temperature and oxygen content on the lattice parameters of the alpha phase was derived and new data obtained on the coefficients of thermal expansion in the different directions of the hcp alpha phase, for Ti-6Al-4V and Ti-6Al-2Sn-4Zr-2Mo-0.08Si.

LPCVD of tungsten by selective deposition on silicon

Beta-phase W, selectively grown at 440C had resistivity 20 micro-ohm cm and maximum layer thickness 100nm. Hydrogen passivation proved essential in this process. Higher deposition temperatures resulted in increased layer thickness but incorporated WSi2 and alpha- phase W. Self limiting W grown on polycrystalline and heavily doped silicon yielded reduced thickness. Boron is involved in the WF6 reduction reaction but phosphorus is not and becomes incorporated in the W layer. The paper establishes an optimised and novel CVD process suited to IC contact technology. A funded technology transfer contract with National Semiconductor Greenock (M Fallon) resulted from this work.

Tungsten Silicide Contacts to Polycrystalline Silicon and Silicon-Germanium Alloys

Novel CVD WSi2 technology with low series and contact resistance in SiGe HBTs was achieved. Specific contact resistance to Si1-xGex with 0

Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.

Performance assessment of nanoscale double- and triple- gate FinFETs

This is the first paper to describe performance assessment of triple and double gate FinFETs for High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) logic technologies is investigated. The impact of gate work-function, spacer width, lateral source/drain doping gradient, fin aspect ratio, fin thickness on device performance, has been analysed in detail and guidelines are presented to meet ITRS specification at 65 and 45 nm nodes. Optimal design of lateral source/drain doping profile can not only effectively control short channel effects, yielding low off-current, but also achieve low values of intrinsic gate delay.