Simulation of a Monolithic Integrated CMOS Preamplifier for Neural Recordings

A monolithic integrated CMOS preamplifier is presented for neural recording applications. Two AC-coupied capacitors are used to eliminate the large and random DC offsets existing in the electrode-electrolyte interface. Diode-connected nMOS transistors with a negative voltage between the gate and source are candidates for the large resistors necessary for the preamplifier. A novel analysis is given to determine the noise power spectral density. Simulation results show that the two-stage CMOS preamplifier in a closed-loop capacitive feedback configuration provides an AC in-band gain of 38.8dB,a DC gain of 0,and an input-referred noise of 277nVmax, integrated from 0. 1Hz to 1kHz. The preamplifier can eliminate the DC offset voltage and has low input-referred noise by novel circuit configuration and theoretical analysis.

Co—Design of Monolithically Integrated Photo—Detectorand Optical—Receiver

A behavioral model of the photodiode is presented．The model describes the relationship between photocurrent and incident optical power，and it also illustrates the impact of the reverse bias to the variation of the junction capacitance．According to this model，the photodiode and a CMOS receiver circuit are simulated and designed simultaneously under a universal circuit simulation environment．

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入

Observation of deep electron states in n-type Al-doped ZnS1-xTex grown by molecular beam epitaxy

Deep level transient spectroscopy (DLTS) technique was used to investigate deep electron states in n-type Al-doped ZnS1-xTex epilayers grown by molecular fiction epitaxy (MBE), Deep level transient Fourier spectroscopy (DLTFS) spectra of the Al-doped ZnS1-xTex (x = 0. 0.017, 0.04 and 0.046. respectively) epilayers reveal that At doping leads to the formation of two electron traps at 0.21 and 0.39 eV below the conduction hand. 1)DLTFS results suggest that in addition to the rules of Te as a component of [lie alloy as well as isoelectronic centers, Te is also involved in the formation of all electron trip, whose energy level relative to the conduction hand decreases a, Te composition increases.

Improvement of CMOS SOS devices characteristics by a modified solid phase epitaxy

CMOS/SOS devices have lower carriers mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly results from the defects of heteroepitaxial silicon film, especially from the defects near Si-Sapphire interface. This paper describes the experiment results of CMOS/SOS devices characteristics improved by a better epitaxial silicon quality which is obtained by a modified solid phase epitaxy.

Dependence of ultra-thin gate oxide reliability on surface cleaning approach

In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H2SO4/H2O2 (SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.

The design of cascaded resistors in a new analog switch two-step ADC architecture

In this paper we introduce a new Half-flash analog switch ADC architecture. And we discuss two methods to design the values of the cascaded resistors which generate the reference voltages. Derailed analysis about the effect of analog switches and comparators on reference voltages, and the methods to set the resistor values and correspond;ng voltage errors are given.

An analysis of the performance of a new high-speed single-way analog switch

This paper introduces a new highspeed single-way analog switch which has both highspeed high-resolution mono-direction analog transmission gate function and high-speed digital logic gate function with normal bipolar technology. The analysis of static and transient switching performances as an analog transmission gate is emphasized in the paper. In order to reduce the plug-in effect on high-speed high-resolution systems, an optimum design scheme is also given. This scheme is to achieve accelerated dynamic response with very low bias power dissipation. The analysis of PSPICE simulation as well as the circuit test results confirms the feasibility of the scheme. Now, the circuit has been applied effectively to the designs of novel highspeed A/D and D/A converters.

Analysis of leakage current in GaAs micro-solar cell arrays

The output characteristics of micro-solar cell arrays are analyzed on the basis of a modified model in which the shunt resistance between cell lines results in current leakage. The modification mainly consists of adding a shunt resistor network to the traditional model. The obtained results agree well with the reported experimental results. The calculation results demonstrate that leakage current in substrate affects seriously the performance of GaAs micro- solar cell arrays. The performance of arrays can be improved by reducing the number of cells per line. In addition, at a certain level of integration, an appropriate space occupancy rate of the single cell is recommended for ensuring high open circuit voltages, and it is more appropriate to set the rates at 80%-90% through the calculation.

Intercellular calcium wave propagation in linear and circuit-like bone cell networks

In the present study, the mechanism of intercellular calcium wave propagation in bone cell networks was identified. By using micro-contact printing and self-assembled monolayer technologies, two types of in vitro bone cell networks were constructed: open-ended linear chains and looped hexagonal networks with precisely controlled intercellular distances. Intracellular calcium responses of the cells were recorded and analysed when a single cell in the network was mechanically stimulated by nano-indentation. The looped cell network was shown to be more efficient than the linear pattern in transferring calcium signals from cell to cell. This phenomenon was further examined by pathway-inhibition studies. Intercellular calcium wave propagation was significantly impeded when extracellular adenosine triphosphate (ATP) in the medium was hydrolysed. Chemical uncoupling of gap junctions, however, did not significantly decrease the transferred distance of the calcium wave in the cell networks. Thus, it is extracellular ATP diffusion, rather than molecular transport through gap junctions, that dominantly mediates the transmission of mechanically elicited intercellular calcium waves in bone cells. The inhibition studies also demonstrated that the mechanical stimulation-induced calcium responses required extracellular calcium influx, whereas the ATP-elicited calcium wave relied on calcium release from the calcium store of the endoplasmic reticulum.

Simulation of micromegas detector by garfield program

In this paper, a batch file which describes the detailed structure and the corresponding physical process of Micro-Mesh Gaseous Structure (Micromegas) detector, the macro commands and the control structures based on the Garfield program has been developed. And using the Garfield program controlled by this batch file, the detector's gain and spatial resolution have been investigated under different conditions. These results obtained by the simulation program not only exhibit the influences of the mesh and drift voltage, the mixture gas proportion, the distance between the mesh cathode and the printed circuit board readout anode, and the Lines Per Inch of the mesh cathode on the gain and spatial resolution of the detector, but also are very important to optimize the design, shorten the experimental period, and save cost during the detector development. Additionally, they also indicate that the Garfield program is a powerful tool for the Micromegas detector design and optimization.

Design and simulation of charge sensitive preamplifier with CMOS FET implemented as feedback capacitor C-fp

In this paper, to design a new preamplifier for optimum performances with charged-particle or heavy-ion detectors, the CMOS FET is implemented as a feedback capacitor C-fp, so that the entire system should be built only with MOSFET. This work is a revolution design because to realize an ASIC for a preamplifier circuit, the capacitor will also be included. We succeed after a simulation to maintain a rise time less than 3 ns, the output resistance less than 94 Omega and the linearity almost good.

Quench Protection Design and Simulation of a 7 Tesla Superconducting Magnet

A 7 Tesla superconducting magnet with a clear warm bore of 156 mm in diameter has been developed for Lanzhou Penning Trap at the Institute of Modern Physics for high precision mass measurement. The magnet is comprised of 9 solenoid coils and operates in persistent mode with a total energy of 2.3 MJ. Due to the considerable amount of energy stored during persistent mode operation, the quench protection system is very important when designing and operating the magnet. A passive protection system based on a subdivided scheme is adopted to protect the superconducting magnet from damage caused by quenching. Cold diodes and resistors are put across the subdivision to reduce both the voltage and temperature hot spots. Computational simulations have been carried in Opera-quench. The designed quench protection circuit and the finite element method model for quench simulations are described; the time changing of temperature, voltage and current decay during the quench process is also analysed.

The effect of annealing treatment on performance of interdiffused organic photovoltaic devices

We fabricated the interdiffused organic photovoltaic devices, which composed of poly (2-methoxy-5-(2'-ethylhexyloxy)-1, 4-phenylenevinylene) (MEH-PPV) and buckminsterfullerene (C-60), by annealing treatment. After annealing, C60 diffused into the MEH-PPV layer, in consequence, MEH-PPV/C-60 interfacial area was increased and their interface became closer proximity. The results lead to reduce reverse-bias saturation current (J(s)), and increase the open-circuit voltage (V-OC) and the short-circuit current (J(SC)).

Effects of thermal annealing on polymer photovoltaic cells with buffer layers and in situ formation of interfacial layer for enhancing power conversion efficiency

We have investigated the effects of thermal annealing before and after cathode deposition on poly(3-hexylthiophene)(P3HT)/[6,6]-phenyl C61-butyric acid methyl ester (PCBM) blend photovoltaic cells with different cathode buffer layers. The introduction of cathode buffer layer such as lithium fluoride (LiF) and calcium oxide (CaO) in pre-annealing cells can increase the open-circuit voltage (V-oc) and the power conversion efficiency (PCE). Post thermal annealing after cathode deposition further enhanced the PCE of the cells with LiF/Al cathode.