Improving DPA and DFA resistance of circuits using asynchronous logic

International audience

Quasi delay insensitive asynchronous circuits for low EMI

International audience

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Post-CMOS compatible high-throughput fabrication of AIN-based piezoelectric microcantilevers

A post-complementary metal oxide semiconductor (CMOS) compatible microfabrication process of piezoelectric cantilevers has been developed. The fabrication process is suitable for standard silicon technology and provides low-cost and high-throughput manufacturing. This work reports design, fabrication and characterization of piezoelectric cantilevers based on aluminum nitride (AlN) thin films synthesized at room temperature. The proposed microcantilever system is a sandwich structure composed of chromium (Cr) electrodes and a sputtered AlN film. The key issue for cantilever fabrication is the growth at room temperature of the AlN layer by reactive sputtering, making possible the innovative compatibility of piezoelectric MEMS devices with CMOS circuits already processed. AlN and Cr have been etched by inductively coupled plasma (ICP) dry etching using a BCl3–Cl2–Ar plasma chemistry. As part of the novelty of the post-CMOS micromachining process presented here, a silicon Si (1 0 0) wafer has been used as substrate as well as the sacrificial layer used to release the microcantilevers. In order to achieve this, the Si surface underneath the structure has been wet etched using an HNA (hydrofluoric acid + nitric acid + acetic acid) based solution. X-ray diffraction (XRD) characterization indicated the high crystalline quality of the AlN film. An atomic force microscope (AFM) has been used to determine the Cr electrode surface roughness. The morphology of the fabricated devices has been studied by scanning electron microscope (SEM). The cantilevers have been piezoelectrically actuated and their out-of-plane vibration modes were detected by vibrometry.

Myelodysplastic Syndrome With Synchronous Gastric Cancer: When The Symptoms Suggest Something Else.

Although myelodysplastic syndromes have a clear definition in theory, the morphologic dysplasia associated with ineffective hematopoiesis may be subtle and difficult to recognize and can commonly be mimicked by systemic conditions, such as infections, autoimmune disorders, nutritional deficiencies, toxic factors and non-hematological malignancies. However, myelodysplastic syndromes may truly coexist with other systemic diseases, which can be masked when the patient's symptoms are attributed exclusively to myelodysplastic syndromes without further investigation. To better illustrate this, we herein describe two cases associated with synchronous gastric cancers.

Synchronous Oral Paracoccidioidomycosis And Pulmonary Tuberculosis In An Immunocompetent Patient.

Paracoccidioidomycosis (PCM) and tuberculosis (TB) are chronic granulomatous infectious diseases, in which the main form of contraction is through inhalation of the microorganism-Paracoccidioides brasiliensis and Mycobacterium tuberculosis. Oral involvement of PCM is observed in up to 70 % of the cases and usually presents clinically as ulcerations with granular surface showing tiny hemorrhagic areas. Oral presentation of TB is rare with prevalence smaller than 0.5 % of all cases. Clinical presentation of oral TB mainly consists of single ulcers with irregular limits and necrotic base. A 70-year-old immunocompetent man presented simultaneously oral PCM and pulmonary TB. Medical history revealed a previous diagnosis of pulmonary TB; however, even under treatment for TB, the patient remained with oral lesions and intense pulmonary fibrosis. The physician requested P. brasiliensis serological analysis, which resulted positive. Although the combination of PCM and TB has been reported in the literature, it is still considered an uncommon condition and their diagnosis may represent a challenge to healthcare professionals because of the similarity between their clinical and radiological presentations.

Engagement of multifocal neural circuits during recall of autobiographical happy events

Happy emotional states have not been extensively explored in functional magnetic resonance imaging studies using autobiographic recall paradigms. We investigated the brain circuitry engaged during induction of happiness by standardized script-driven autobiographical recall in 11 healthy subjects (6 males), aged 32.4 ± 7.2 years, without physical or psychiatric disorders, selected according to their ability to vividly recall personal experiences. Blood oxygen level-dependent (BOLD) changes were recorded during auditory presentation of personal scripts of happiness, neutral content and negative emotional content (irritability). The same uniform structure was used for the cueing narratives of both emotionally salient and neutral conditions, in order to decrease the variability of findings. In the happiness relative to the neutral condition, there was an increased BOLD signal in the left dorsal prefrontal cortex and anterior insula, thalamus bilaterally, left hypothalamus, left anterior cingulate gyrus, and midportions of the left middle temporal gyrus (P < 0.05, corrected for multiple comparisons). Relative to the irritability condition, the happiness condition showed increased activity in the left insula, thalamus and hypothalamus, and in anterior and midportions of the inferior and middle temporal gyri bilaterally (P < 0.05, corrected), varying in size between 13 and 64 voxels. Findings of happiness-related increased activity in prefrontal and subcortical regions extend the results of previous functional imaging studies of autobiographical recall. The BOLD signal changes identified reflect general aspects of emotional processing, emotional control, and the processing of sensory and bodily signals associated with internally generated feelings of happiness. These results reinforce the notion that happiness induction engages a wide network of brain regions.

Fully Connected PLL Networks: How Filter Determines the Number of Nodes

Synchronization plays an important role in telecommunication systems, integrated circuits, and automation systems. Formerly, the masterslave synchronization strategy was used in the great majority of cases due to its reliability and simplicity. Recently, with the wireless networks development, and with the increase of the operation frequency of integrated circuits, the decentralized clock distribution strategies are gaining importance. Consequently, fully connected clock distribution systems with nodes composed of phase-locked loops (PLLs) appear as a convenient engineering solution. In this work, the stability of the synchronous state of these networks is studied in two relevant situations: when the node filters are first-order lag-lead low-pass or when the node filters are second-order low-pass. For first-order filters, the synchronous state of the network shows to be stable for any number of nodes. For second-order filter, there is a superior limit for the number of nodes, depending on the PLL parameters. Copyright (C) 2009 Atila Madureira Bueno et al.

Power imbalance application region method for distributed synchronous generator anti-islanding protection design and evaluation

This paper presents a novel graphical approach to adjust and evaluate frequency-based relays employed in anti-islanding protection schemes of distributed synchronous generators, in order to meet the anti-islanding and abnormal frequency variation requirements, simultaneously. The proposed method defines a region in the power mismatch space, inside which the relay non-detection zone should be located, if the above-mentioned requirements must be met. Such region is called power imbalance application region. Results show that this method can help protection engineers to adjust frequency-based relays to improve the anti-islanding capability and to minimize false operation occurrences, keeping the abnormal frequency variation utility requirements satisfied. Moreover, the proposed method can be employed to coordinate different types of frequency-based relays, aiming at improving overall performance of the distributed generator frequency protection scheme. (C) 2011 Elsevier B.V. All rights reserved.

Fuzzy risk index for power transformer failures due to external short-circuits

A novel methodology to assess the risk of power transformer failures caused by external faults, such as short-circuit, taking the paper insulation condition into account, is presented. The risk index is obtained by contrasting the insulation paper condition with the probability that the transformer withstands the short-circuit current flowing along the winding during an external fault. In order to assess the risk, this probability and the value of the degree of polymerization of the insulating paper are regarded as inputs of a type-2 fuzzy logic system (T2-FLS), which computes the fuzzy risk level. A Monte Carlo simulation has been used to find the survival function of the currents flowing through the transformer winding during a single-phase or a three-phase short-circuit. The Roy Billinton Test System and a real power system have been used to test the results. (C) 2008 Elsevier B.V. All rights reserved.

Comparison Between Voltage Control Structures of Synchronous Machines

This paper compares the behaviour of two different control structures of automatic voltage regulators of synchronous machines equipped with static excitation systems. These systems have a fully controlled thyristor bridge that supplies DC current to the rotor winding. The rectifier bridge is fed by the stator terminals through a step-down transformer. The first control structure, named ""Direct Control"", has a single proportional-integral (PI) regulator that compares stator voltage setpoint with measured voltage and acts directly on the thyristor bridge`s firing angle. This control structure is usually employed in commercial excitation systems for hydrogenerators. The second structure, named ""Cascade Control"", was inspired on control loops of commercial DC motor drives. Such drives employ two PIs in a cascade arrangement, the external PI deals with the motor speed while the internal one regulates the armature current. In the adaptation proposed, the external PI compares setpoint with the actual stator voltage and produces the setpoint to the internal PI-loop which controls the field current.

Modeling and Filtering Double-Frequency Jitter in One-Way Master-Slave Chain Networks

One-way master-slave (OWMS) chain networks are widely used in clock distribution systems due to their reliability and low cost. As the network nodes are phase-locked loops (PLLs), double-frequency jitter (DFJ) caused by their phase detectors appears as an impairment to the performance of the clock recovering process found in communication systems and instrumentation applications. A nonlinear model for OWMS chain networks with P + 1 order PLLs as slave nodes is presented, considering the DFJ. Since higher order filters are more effective in filtering DFJ, the synchronous state stability conditions for an OWMS chain network with third-order nodes are derived, relating the loop gain and the filter coefficients. By using these conditions, design examples are discussed.

Using bifurcations in the determination of lock-in ranges for third-order phase-locked loops

Transmission and switching in digital telecommunication networks require distribution of precise time signals among the nodes. Commercial systems usually adopt a master-slave (MS) clock distribution strategy building slave nodes with phase-locked loop (PLL) circuits. PLLs are responsible for synchronizing their local oscillations with signals from master nodes, providing reliable clocks in all nodes. The dynamics of a PLL is described by an ordinary nonlinear differential equation, with order one plus the order of its internal linear low-pass filter. Second-order loops are commonly used because their synchronous state is asymptotically stable and the lock-in range and design parameters are expressed by a linear equivalent system [Gardner FM. Phaselock techniques. New York: John Wiley & Sons: 1979]. In spite of being simple and robust, second-order PLLs frequently present double-frequency terms in PD output and it is very difficult to adapt a first-order filter in order to cut off these components [Piqueira JRC, Monteiro LHA. Considering second-harmonic terms in the operation of the phase detector for second order phase-locked loop. IEEE Trans Circuits Syst [2003;50(6):805-9; Piqueira JRC, Monteiro LHA. All-pole phase-locked loops: calculating lock-in range by using Evan`s root-locus. Int J Control 2006;79(7):822-9]. Consequently, higher-order filters are used, resulting in nonlinear loops with order greater than 2. Such systems, due to high order and nonlinear terms, depending on parameters combinations, can present some undesirable behaviors, resulting from bifurcations, as error oscillation and chaos, decreasing synchronization ranges. In this work, we consider a second-order Sallen-Key loop filter [van Valkenburg ME. Analog filter design. New York: Holt, Rinehart & Winston; 1982] implying a third order PLL The resulting lock-in range of the third-order PLL is determined by two bifurcation conditions: a saddle-node and a Hopf. (C) 2008 Elsevier B.V. All rights reserved.

Reachability of the synchronous state in a mutually connected PLL network

Second-order phase locked loops (PLLs) are devices that are able to provide synchronization between the nodes in a network even under severe quality restrictions in the signal propagation. Consequently, they are widely used in telecommunication and control. Conventional master-slave (M-S) clock-distribution systems are being, replaced by mutually connected (MC) ones due to their good potential to be used in new types of application such as wireless sensor networks, distributed computation and communication systems. Here, by using an analytical reasoning, a nonlinear algebraic system of equations is proposed to establish the existence conditions for the synchronous state in an MC PLL network. Numerical experiments confirm the analytical results and provide ideas about how the network parameters affect the reachability of the synchronous state. The phase-difference oscillation amplitudes are related to the node parameters helping to design PLL neural networks. Furthermore, estimation of the acquisition time depending on the node parameters allows the performance evaluation of time distribution systems and neural networks based on phase-locked techniques. (c) 2008 Elsevier GmbH. All rights reserved.

Mutually connected phase-locked loop networks: dynamical models and design parameters

Distribution of timing signals is an essential factor for the development of digital systems for telecommunication networks, integrated circuits and manufacturing automation. Originally, this distribution was implemented by using the master-slave architecture with a precise master clock generator sending signals to phase-locked loops (PLL) working as slave oscillators. Nowadays, wireless networks with dynamical connectivity and the increase in size and operation frequency of the integrated circuits suggest that the distribution of clock signals could be more efficient if mutually connected architectures were used. Here, mutually connected PLL networks are studied and conditions for synchronous states existence are analytically derived, depending on individual node parameters and network connectivity, considering that the nodes are nonlinear oscillators with nonlinear coupling conditions. An expression for the network synchronisation frequency is obtained. The lock-in range and the transmission error bounds are analysed providing hints to the design of this kind of clock distribution system.