Improving DPA and DFA resistance of circuits using asynchronous logic

International audience

In this communication, we propose to present the very recent research works we carried-out on design methodologies for secure chips by improving their resistance against two major types of attacks: differential power analysis (DPA) and differential fault analysis (DFA). The circuit technology investigated to improve the resistance in terms of DPA and DFA is asynchronous logic. The strength of the proposed methodologies is to jointly harden the circuits with respect to both types of attacks. Moreover, the hardening techniques apply at design time and the benefits are verified by simulation before fabrication.The presentation first introduces the basic principles of asynchronous logic, highlighting the differences with the synchronous logic especially in terms of information leakage sources. We show why asynchronous logic is likely to enable us to improve chip resistance against DPA and DFA. The second part of the talk is devoted to DPA. We show how we theoretically model the source of leakage enabling DPA-based attacks to occur. This theoretical model of leakage is the criterion we are optimising in order to improve the chip resistance. Asynchronous logic is an efficient mean to reach this goal. The third part of the presentation is focused on DFA. Our approach is aimed at theoretically modelling the origin of the leakage and at building the defence accordingly. Therefore, we define a sensitivity criterion of the circuit which quantifies the probability for every cell of the circuit to propagate a fault. Computing this criterion enables us to identify the most sensitive parts of the circuits that must be protected, and also helps to specify protection strategies at design time. In a concluding part, we report on the design flow of DPA and DFA resistant circuits and on the results obtained with prototype chips. We finally draw some conclusion and introduce some prospective works.