Diagnostic accuracy and clinical management by realtime teledermatology. Results from the Northern Ireland arms of the UK Multicentre Teledermatology Trial

Diagnostic accuracy and management recommendations of realtime teledermatology consultations using low-cost telemedicine equipment were evaluated. Patients were seen by a dermatologist over a video-link and a diagnosis and treatment plan were recorded. This was followed by a face-to-face consultation on the same day to confirm the earlier diagnosis and management plan. A total of 351 patients with 427 diagnoses participated. Sixty-seven per cent of the diagnoses made over the video-link agreed with the face-to-face diagnosis. Clinical management plans were recorded for 214 patients with 252 diagnoses. For this cohort, 44% of the patients were seen by the same dermatologist at both consultations, while 56% were seen by a different dermatologist. In 64% of cases the same management plan was recommended at both consultations; a sub-optimum treatment plan was recommended in 8% of cases; and in 9% of cases the video-link management plans were judged to be inappropriate. In 20% of cases the dermatologist was unable to recommend a suitable management plan by video-link. There were significant differences in the ability to recommend an optimum management plan by video-link when a different dermatologist made the reference management plan. The results indicate that a high proportion of dermatological conditions can be successfully managed by realtime teledermatology.

Preliminary results from the Northern Ireland arms of the UK Multicentre Teledermatology Trial:is clinical management by realtime teledermatology possible?

Results from phase 1 of the UK Multicentre Teledermatology Trial demonstrated the diagnostic accuracy of realtime teledermatology using low-cost equipment. Phase 2 of the trial aimed to assess its effectiveness as a management tool for dermatological disease. Teledermatology consultations were organized between two health centres and two hospitals in Northern Ireland using low-cost videoconferencing equipment. For 205 patients seen by a dermatologist over the video-link a diagnosis and management plan were recorded. A subsequent face-to-face consultation was arranged on the same day to confirm the diagnosis and treatment regime. A comparison of these management plans revealed that the same plan was recommended in 64% of cases; the teledermatologist was unable to advocate a suitable management plan in 19% of cases; a suboptimal treatment plan was suggested by the teledermatologist in 6% of cases; and in 11% of cases, the teledermatologist suggested an inappropriate treatment plan. These findings indicate that appropriate clinical management was possible in approximately two-thirds of dermatology consultations via the video-link.

Patient satisfaction with realtime teledermatology in Northern Ireland

Teledermatology consultations were organized between two health centers and two hospitals in Northern Ireland using low-cost videoconferencing equipment. A prospective study of patient satisfaction was carried out. Following each teleconsultation, patients were asked to complete a questionnaire assessing their satisfaction with the service. Over 22 months, 334 patients were seen by a dermatologist over the video-link, and 292 patients (87%) completed the 16-item questionnaire. Patients reported universal satisfaction with the technical aspects of teledermatology. The quality of both the audio and the display was highly acceptable to patients. Personal experiences of the teledermatology consultation were also favourable: 85% felt comfortable using the video-link. The benefits of teledermatology were generally recognized: 88% of patients thought that a teleconsultation could save time. Patients found the teledermatology consultation to be as acceptable as the conventional dermatology consultation. These findings suggest overall patient satisfaction with realtime teledermatology.

From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

VLSI architectures for vector quantization

The real time implementation of an efficient signal compression technique, Vector Quantization (VQ), is of great importance to many digital signal coding applications. In this paper, we describe a new family of bit level systolic VLSI architectures which offer an attractive solution to this problem. These architectures are based on a bit serial, word parallel approach and high performance and efficiency can be achieved for VQ applications of a wide range of bandwidths. Compared with their bit parallel counterparts, these bit serial circuits provide better alternatives for VQ implementations in terms of performance and cost. © 1995 Kluwer Academic Publishers.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

Bit-Level systolic architectures for high performance IIR filtering

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware. © 1989 Kluwer Academic Publishers.

A bit-level systolic architecture for implementing a VQ tree search

A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system. © 1990 Kluwer Academic Publishers.

Fast VLSI algorithms for division and square root

Real time digital signal processing demands high performance implementations of division and square root. This can only be achieved by the design of fast and efficient arithmetic algorithms which address practical VLSI architectural design issues. In this paper, new algorithms for division and square root are described. The new schemes are based on pre-scaling the operands and modifying the classical SRT method such that the result digits and the remainders are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance exceeds that of the SRT methods. The hardware cost for higher radices is considerably more than that of the SRT methods but for many applications, this is not prohibitive. A system of equations is presented which enables both an analysis of the method for any radix and the parameters of implementations to be easily determined. This is illustrated for the case of radix 2 and radix 4. In addition, a highly regular array architecture combining the division and square root method is described. © 1994 Kluwer Academic Publishers.

Rijndael FPGA implementations utilising look-up tables

This paper presents single-chip FPGA Rijndael algorithm implementations of the Advanced Encryption Standard (AES) algorithm, Rijndael. In particular, the designs utilise look-up tables to implement the entire Rijndael Round function. A comparison is provided between these designs and similar existing implementations. Hardware implementations of encryption algorithms prove much faster than equivalent software implementations and since there is a need to perform encryption on data in real time, speed is very important. In particular, Field Programmable Gate Arrays (FPGAs) are well suited to encryption implementations due to their flexibility and an architecture, which can be exploited to accommodate typical encryption transformations. In this paper, a Look-Up Table (LUT) methodology is introduced where complex and slow operations are replaced by simple LUTs. A LUT-based fully pipelined Rijndael implementation is described which has a pre-placement performance of 12 Gbits/sec, which is a factor 1.2 times faster than an alternative design in which look-up tables are utilised to implement only one of the Round function transformations, and 6 times faster than other previous single-chip implementations. Iterative Rijndael implementations based on the Look-Up-Table design approach are also discussed and prove faster than typical iterative implementations.

Programmable image processing chip

A new high performance, programmable image processing chip targeted at video and HDTV applications is described. This was initially developed for image small object recognition but has much broader functional application including 1D and 2D FIR filtering as well as neural network computation. The core of the circuit is made up of an array of twenty one multiplication-accumulation cells based on systolic architecture. Devices can be cascaded to increase the order of the filter both vertically and horizontally. The chip has been fabricated in a 0.6 µ, low power CMOS technology and operates on 10 bit input data at over 54 Megasamples per second. The introduction gives some background to the chip design and highlights that there are few other comparable devices. Section 2 gives a brief introduction to small object detection. The chip architecture and the chip design will be described in detail in the later sections.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

The link between logic, mathematics and imagination: evidence from children with developmental dyscalculia and mathematically gifted children

This study examined performance on transitive inference problems in children with developmental dyscalculia (DD), typically developing controls matched on IQ, working memory and reading skills, and in children with outstanding mathematical abilities. Whereas mainstream approaches currently consider DD as a domain-specific deficit, we hypothesized that the development of mathematical skills is closely related to the development of logical abilities, a domain-general skill. In particular, we expected a close link between mathematical skills and the ability to reason independently of one's beliefs. Our results showed that this was indeed the case, with children with DD performing more poorly than controls, and high maths ability children showing outstanding skills in logical reasoning about belief-laden problems. Nevertheless, all groups performed poorly on structurally equivalent problems with belief-neutral content. This is in line with suggestions that abstract reasoning skills (i.e. the ability to reason about content without real-life referents) develops later than the ability to reason about belief-inconsistent fantasy content.A video abstract of this article can be viewed at http://www.youtube.com/watch?v=90DWY3O4xx8.

More than just a ‘nasty’ decade::Classifying the popular in the 1980s

This chapter moves beyond studies of the 'video nasties' to consider the BBFC's approach to other films, including popualr blockbusters like Return of the Jedi and Raiders of the Lost Ark. This work draws attention to emergent discourses at the Board relating to children, the importance of the teen audience and violence in a variety of generic formats.

Distinguished algebraic semantics for t-norm based fuzzy logics:Methods and algebraic equivalencies

This paper is a contribution to Mathematical fuzzy logic, in particular to the algebraic study of t-norm based fuzzy logics. In the general framework of propositional core and ?-core fuzzy logics we consider three properties of completeness with respect to any semantics of linearly ordered algebras. Useful algebraic characterizations of these completeness properties are obtained and their relations are studied. Moreover, we concentrate on five kinds of distinguished semantics for these logics-namely the class of algebras defined over the real unit interval, the rational unit interval, the hyperreals (all ultrapowers of the real unit interval), the strict hyperreals (only ultrapowers giving a proper extension of the real unit interval) and finite chains, respectively-and we survey the known completeness methods and results for prominent logics. We also obtain new interesting relations between the real, rational and (strict) hyperreal semantics, and good characterizations for the completeness with respect to the semantics of finite chains. Finally, all completeness properties and distinguished semantics are also considered for the first-order versions of the logics where a number of new results are proved. © 2009 Elsevier B.V. All rights reserved.