Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

The new exploration for proton-implanted silicon: the conversion of a surface-region-purification-induced p-n junction into a p-i-n electrical structure approaching silicon on insulator

A surface-region-purification-induced p-n junction, a puzzle discovered at Brookhaven National Laboratory, in a silicon-on-defect-layer (SODL) material has been explored by carrying out various annealing conditions and subsequent measurements on electrical properties. The origin of the pn junction has been experimentally investigated. Furthermore, the p-n junction has been transformed into a p-i-n electrical structure by adding a high temperature annealing process to the previously used SODL procedure, making the SODL material approach silicon on insulator (SOI). The control of the initial oxygen amount in the silicon material is suggested to be critical for the experimental results.

A new interface anisotropic potential of zinc-blende semiconductor interface induced by lattice mismatch

A new interface anisotropic potential, which is proportional to the lattice mismatch of interfaces and has no fitting parameter, has been deduced for (001) zinc-blende semiconductor interfaces. The comparison with other interface models is given for GaAs/AlAs and GaAs/InAs interfaces. The strong influence of the interface anisotropic potential on the inplane optical anisotropy of GaAs/AlGaAs low dimensional structures is demonstrated theoretically within the envelope function approximation.

Analysis and Simulation of S-shaped Waveguide in Silicon-on-insulator

The simulation and analysis of S-shaped waveguide bend are presented.Bend radius larger than 30 mm assures less than 0.5 dB radiation loss for a 4-μm-wide silicon-on-insulator waveguide bend with 2-μm etch depth.Intersection angle greater than 20° provides negligible crosstalk (＜-30 dB) and very low insertion loss.Any reduction in bend radius and intersection angle is at the cost of the degradation of characteristics of bent waveguide and intersecting waveguide, respectively.

High-speed electrooptical VOA integrated in silicon-on-insulator

In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) inte-grated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption toachieve attenuation. Beam propagation method (BPM) and two-dimensional semiconductor device simu-lation tool PISCES-Ⅱ were used to analyze the dc and transient characteristics of the device. The devicehas a response time (including rise time and fall time) less than 200 ns, much faster than the thermoopticand micro-electromechanical systems (MEMSs) based VOAs.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Electrical characteristics of copper phthalocyanine thin-film transistors with polyamide-6/polytetrafluoroethylene gate insulator

Polyamide- 6(PA 6)/polytetrafluoroethylene is studied as a potential gate dielectric for flexible organic thin film transistors. The same method used for the formation of organic semiconductor and gate dielectric films greatly simplifies the fabrication process of devices. The fabricated transistors show good electrical characteristics. Ambipolar behaviour is observed even when the device is operated in air.

Copper phthalocyanine organic thin-film transistors with calcium fluoride gate insulator

We report the fabrication of organic thin-film transistors (OTFTs) with copper phthalocyanine (CuPc) as the semiconductor and calcium fluoride (CaF2) as the gate dielectric on the glass substrate. The fabricated transistors show a gate voltage dependent carrier field effect mobility that ranges from 0.001 to 0.5 cm(2) V-1 s(-1). In the devices, the CaF2 dielectric is formed by thermal evaporation; thus OTFTs with a top-gate structure can be fabricated. This provides a convenient way to produce high-performance OTFTs on a large scale and should be useful for the integration of organic displays.

Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

First principles simulation of amorphous silicon bulk, interfaces, and nanowires for photovoltaics

Amorphous silicon has become the material of choice for many technologies, with major applications in large area electronics: displays, image sensing and thin film photovoltaic cells. This technology development has occurred because amorphous silicon is a thin film semiconductor that can be deposited on large, low cost substrates using low temperature. In this thesis, classical molecular dynamics and first principles DFT calculations have been performed to generate structural models of amorphous and hydrogenated amorphous silicon and interfaces of amorphous and crystalline silicon, with the ultimate aim of understanding the photovoltaic properties of core-shell crystalline amorphous Si nanowire structures. We have shown, unexpectedly, from the simulations, that our understanding of hydrogenated bulk a-Si needs to be revisited, with our robust finding that when fully saturated with hydrogen, bulk a-Si exhibits a constant optical energy gap, irrespective of the hydrogen concentration in the sample. Unsaturated a-Si:H, with a lower than optimum hydrogen content, shows a smaller optical gap, that increases with hydrogen content until saturation is reached. The mobility gaps obtained from an analysis of the electronic states show similar behavior. We also obtained that the optical and mobility gaps show a volcano curve as the H content is varied from 7% (undersaturation) to 18% (mild oversaturation). In the case of mild over saturation, the mid-gap states arise exclusively from an increase in the density of strained Si-Si bonds. Analysis of our structures shows the extra H atoms in this case form a bridge between neighboring silicon atoms which increases the corresponding Si-Si distance and promotes bond length disorder in the sample. That has the potential to enhance the Staebler-Wronski effect. Planar interface models of amorphous-crystalline silicon have been generated in Si (100), (110) and (111) surfaces. The interface models are characterized by structure, RDF, electronic density of states and optical absorption spectrum. We find that the least stable (100) surface will result in the formation of the thickest amorphous silicon layer, while the most stable (110) surface forms the smallest amorphous region. We calculated for the first time band offsets of a-Si:H/c-Si heterojunctions from first principles and examined the influence of different surface orientations and amorphous layer thickness on the offsets and implications for device performance. The band offsets depend on the amorphous layer thickness and increase with thickness. By controlling the amorphous layer thickness we can potentially optimise the solar cell parameters. Finally, we have successfully generated different amorphous layer thickness of the a-Si/c-Si and a-Si:H/c-Si 5 nm nanowires from heat and quench. We perform structural analysis of the a-Si-/c-Si nanowires. The RDF, Si-Si bond length distributions, and the coordination number distributions of amorphous regions of the nanowires reproduce similar behaviour compared to bulk amorphous silicon. In the final part of this thesis we examine different surface terminating chemical groups, -H, - OH and –NH2 in (001) GeNW. Our work shows that the diameter of Ge nanowires and the nature of surface terminating groups both play a significant role in both the magnitude and the nature of the nanowire band gaps, allowing tuning of the band gap by up to 1.1 eV. We also show for the first time how the nanowire diameter and surface termination shifts the absorption edge in the Ge nanowires to longer wavelengths. Thus, the combination of nanowire diameter and surface chemistry can be effectively utilised to tune the band gaps and thus light absorption properties of small diameter Ge nanowires.

Material effects on stress-induced defect generation in trenched silicon-on-insulator structures

We have investigated the influence of the material properties of the silicon device layer on the generation of defects, and in particular slip dislocations, in trenched and refilled fusion-bonded silicon-on-insulator structures. A strong dependence of the ease of slip generation on the type of dopant species was observed, with the samples falling into three basic categories; heavily boron-doped silicon showed ready slip generation, arsenic and antimony-doped material was fairly resistant to slip, while silicon moderately or lightly doped with phosphorous or boron gave intermediate behavior. The observed behavior appears to be controlled by differences in the dislocation generation mechanism rather than by dislocation mobility. The introduction of an implanted buried layer at the bonding interface was found to result in an increase in slip generation in the silicon, again with a variation according to the dopant species. Here, the greatest slip occurred for both boron and antimony-implanted samples. The weakening of the implanted material may be related to the presence of a band of precipitates observed in the silicon near the bonding interface. (C) 2001 The Electrochemical Society.

Fabrication of Sub-micron Active Layer SSOI Substrates using Ion Splitting and Wafer Bonding Technologies

This paper reports the fabrication of SSOI (Silicon on Silicide On Insulator) substrates with active silicon regions only 0.5mum thick, incorporating LPCVD low resistivity tungsten silicide (WSix) as the buried layer. The substrates were produced using ion splitting and two stages of wafer bonding. Scanning acoustic microscope imaging confirmed that the bond interfaces are essentially void-free. These SSOI wafers are designed to be employed as substrates for mm-wave reflect-array diodes, and the required selective etch technology is described together with details of a suitable device.