Control-limited perfect state transfer, quantum stochastic resonance, and many-body entangling gate in imperfect qubit registers

We propose a protocol for perfect quantum state transfer that is resilient to a broad class of realistic experimental imperfections, including noise sources that could be modeled either as independent Markovian baths or as certain forms of spatially correlated environments. We highlight interesting connections between the fidelity of state transfer and quantum stochastic resonance effects. The scheme is flexible enough to act as an effective entangling gate for the generation of genuine multipartite entanglement in a control-limited setting. Possible experimental implementations using superconducting qubits are also briefly discussed.

The control of wave energy converters using active bipolar damping

A novel method for controlling wave energy converters using active bipolar damping is described and compared with current control methods. The performance of active bipolar damping is modelled numerically for two distinct types of wave energy converter and it is found that in both cases the power capture can be significantly increased relative to optimal linear damping. It is shown that this is because active bipolar damping has the potential for providing a quasi-spring or quasi-inertia, which improves the wave energy converter's tuning and amplitude of motion, resulting in the increase in power capture observed. The practical implementation of active bipolar damping is also discussed. It is noted that active bipolar damping does not require a reactive energy store and thereby reduces the cost and eliminates losses due to the cycling of reactive energy. It is also noted that active bipolar damping could be implemented using a single constant pressure double-acting hydraulic cylinder and so potentially represents a simple, efficient, robust and economic solution to the control of wave energy converters.

Two Arginine-Glutamate Ionic Locks Near the Extracellular Surface of FFAR1 Gate Receptor Activation

Activation of a number of class A G protein-coupled receptors (GPCRs) is thought to involve two molecular switches, a rotamer toggle switch within the transmembrane domain and an ionic lock at the cytoplasmic surface of the receptor; however, the mechanism by which agonist binding changes these molecular interactions is not understood. Importantly, 80% of GPCRs including free fatty acid receptor 1 (FFAR1) lack the complement of amino acid residues implicated in either or both of these two switches; the mechanism of activation of these GPCRs is therefore less clear. By homology modeling, we identified two Glu residues (Glu-145 and Glu-172) in the second extracellular loop of FFAR1 that form putative interactions individually with two transmembrane Arg residues (Arg-183(5.39) and Arg-258(7.35)) to create two ionic locks. Molecular dynamics simulations showed that binding of agonists to FFAR1 leads to breakage of these Glu-Arg interactions. In mutagenesis experiments, breakage of these two putative interactions by substituting Ala for Glu-145 and Glu-172 caused constitutive receptor activation. Our results therefore reveal a molecular switch for receptor activation present on the extracellular surface of FFAR1 that is broken by agonist binding. Similar ionic locks between the transmembrane domains and the extracellular loops may constitute a mechanism common to other class A GPCRs also.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.

Impact of gate-source/drain channel architecture on the performance of an operational transconductance amplifier (OTA)

In this work, we report on the significance of gate-source/drain extension region (also known as underlap design) optimization in double gate (DG) FETs to improve the performance of an operational transconductance amplifier (OTA). It is demonstrated that high values of intrinsic voltage gain (A(VO_OTA)) > 55 dB and unity gain frequency (f(T_OTA)) similar to 57 GHz in a folded cascode OTA can be achieved with gate-underlap channel design in 60 nm DG MOSFETs. These values correspond to 15 dB improvement in A(VO_OTA) and three fold enhancement in f(T_OTA) over a conventional non-underlap design. OTA performance based on underlap single gate SOI MOSFETs realized in ultra-thin body (UTB) and ultra-thin body BOX (UTBB) technologies is also evaluated. A(VO_OTA) values exhibited by a DG MOSFET-based OTA are 1.3-1.6 times higher as compared to a conventional UTB/UTBB single gate OTA. f(T_OTA) values for DG OTA are 10 GHz higher for UTB OTAs whereas a twofold improvement is observed with respect to UTBB OTAs. The simultaneous improvement in A(VO_OTA) and f(T_OTA) highlights the usefulness of underlap channel architecture in improving gain-bandwidth trade-off in analog circuit design. Underlap channel OTAs demonstrate high degree of tolerance to misalignment/oversize between front and back gates without compromising the performance, thus relaxing crucial process/technology-dependent parameters to achieve 'idealized' DG MOSFETs. Results show that underlap OTAs designed with a spacer-to-straggle (s/sigma) ratio of 3.2 and operated below a bias current (IBIAS) of 80 mu A demonstrate optimum performance. The present work provides new opportunities for realizing future ultra-wide band OTA design with underlap DG MOSFETs.