When is `partial' adequate? A logic-based proof technique using partial specifications

A technique is presented for ascertaining when a (finite-state) partial process specification is adequate, in the sense of being specified enough, for contexts in which it is to be used. The method relies on the automatic generation of a modal formula from the partial specification; if the remainder of the network satisfies this formula, then any process that meets the specification is guaranteed to ensure correct behavior of the overall system. Using the results, the authors develop compositional proof rules for establishing the correctness of networks of parallel processes and illustrate their use with several examples

An automatic step adjustment method for average power analysis technique used in fiber amplifiers

An automatic step adjustment (ASA) method for average power analysis (APA) technique used in fiber amplifiers is proposed in this paper for the first time. In comparison with the traditional APA technique, the proposed method has suggested two unique merits such as a higher order accuracy and an ASA mechanism, so that it can significantly shorten the computing time and improve the solution accuracy. A test example demonstrates that, by comparing to the APA technique, the proposed method increases the computing speed by more than a hundredfold under the same errors. By computing the model equations of erbium-doped fiber amplifiers, the numerical results show that our method can improve the solution accuracy by over two orders of magnitude at the same amplifying section number. The proposed method has the capacity to rapidly and effectively compute the model equations of fiber Raman amplifiers and semiconductor lasers. (c) 2006 Optical Society of America

Fast calculation technique for scattering in T-matrix method

In scattering calculations using the T-matrix method, the calculation of the T-matrix involves multiplication and inversion of matrices. These two types of matrix operations are time-consuming, especially for the matrices with large size. Petrov et al. [D. Petrov, Y. Shkuratov, G. Videen, Opt. Lett. 32 (2007) 1168] proposed an optimized matrix inversion technique, which suggests the inversion of two matrices, each of which contains half the number of rows. This technique reduces time-consumption significantly. On the basis of this approach, we propose another fast calculation technique for scattering in the T-matrix method, which obtains the scattered fields through carrying out only the operations between matrices and the incident field coefficient. Numerical results show that this technique can decrease time-consumption by more than half that of the optimized matrix inversion technique by Petrov et al. (c) 2008 Elsevier B.V. All rights reserved.

Real-time non-destructive testing of dynamic holograms in doubly-doped LiNbO3 crystals using phase-conjugate technique

Nankai University

DELINEATION OF DEFECTS IN SIMOX STRUCTURES USING A CHEMICAL ETCHING TECHNIQUE

Residual defects in the overlayer of fully annealed SIMOX material have been studied by means of a chemical etching technique. The etching procedure has been calibrated and an optimum recipe is reported. Observations using optical microscopy and transmission electron microscopy have been used to quantify the defect densities and good agreement between the two techniques has been established, confirming that the optimised chemical etching process can be used with confidence to determine the dislocation density for values < 10(7) cm-2.

METASTABLE DEFECT IN AMORPHOUS-SILICON SOLAR-CELLS INVESTIGATED BY JUNCTION RECOVERY TECHNIQUE

The effect of metastable defects caused by light soaking and carrier injection on the transport of carriers in undoped a-Si:H has been investigated by a junction recovery technique. The experiments show that after light soaking or carrier injection the product of mu-p-tau-p decreases, but no detectable change in the distribution of shallow valence band tail states was found.

Lapping technique of InP single crystal wafer

The wafer processing of Indium Phosphide (InP) is so important that it is getting more and more attentions. Lapping is a basic step just following the ingot cutting. In this paper, the influences of various processing parameters on the lapped wafer quality and lapping rate have been checked, the double-crystal X-ray diffraction results about lapped wafers also were presented here. According to the experimental results, the optimum lapping conditions have been obtained.

ALKALINE POLISHING OF INP USING DOUBLE-POURING TECHNIQUE

于2010-11-17批量导入

A STUDY OF THE COMPOSITION DISTRIBUTION AT THE TI/AL2O3 INTERFACE USING THE MCS(+)-SIMS TECHNIQUE

In this article, the MCs(+)-SIMS technique has been used to characterize Ti/Al2O3 metal/insulator interfaces. Our experiment shows that by detecting MCs(+) secondary ions, the matrix and interface effects are reduced, and good depth profiles have been obtained. The experimental result also shows that with the increase of the annealing temperature (RT, 300 degrees C, 600 degrees C, 850 degrees C), the interface gets broadened gradually, indicating diffusion and reaction take place at the interface, and the interface reaction is enhanced with the increase in annealing temperature. When the temperature increases, the AlCs+ signal forms two plateaus in the Ti layer, indicating Al from the decomposition of Al2O3 diffuses into the Ti layer and exists as two new forms (phases). Also, with the increase of the annealing temperature, oxygen diffuses into the Ti layer gradually, and makes the O signal in the Ti layer increase significantly in the 850 degrees C annealed sample.

A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.