Antropologia e psicoterapia

Tese apresentada à Universidade Fernando Pessoa como parte dos requisitos para obtenção do grau de Doutor em Ciências Sociais, especialidade em Antropologia

Pratiques d’infirmière clinicienne et obésité

Tese apresentada à Universidade Fernando Pessoa como parte dos requisitos para obtenção do grau de Doutor em Ciências Sociais, especialidade em Psicologia

Hybrid integration and packaging of grating-coupled silicon photonics

This thesis covers both the packaging of silicon photonic devices with fiber inputs and outputs as well as the integration of laser light sources with these same devices. The principal challenge in both of these pursuits is coupling light into the submicrometer waveguides that are the hallmark of silicon-on-insulator (SOI) systems. Previous work on grating couplers is leveraged to design new approaches to bridge the gap between the highly-integrated domain of silicon, the Interconnected world of fiber and the active region of III-V materials. First, a novel process for the planar packaging of grating couplers with fibers is explored in detail. This technology allows the creation of easy-to-use test platforms for laser integration and also stands on its own merits as an enabling technology for next-generation silicon photonics systems. The alignment tolerances of this process are shown to be well-suited to a passive alignment process and for wafer-scale assembly. Furthermore, this technology has already been used to package demonstrators for research partners and is included in the offerings of the ePIXfab silicon photonics foundry and as a design kit for PhoeniX Software’s MaskEngineer product. After this, a process for hybridly integrating a discrete edge-emitting laser with a silicon photonic circuit using near-vertical coupling is developed and characterized. The details of the various steps of the design process are given, including mechanical, thermal, optical and electrical steps. The interrelation of these design domains is also discussed. The construction process for a demonstrator is outlined, and measurements are presented of a series of single-wavelength Fabry-Pérot lasers along with a two-section laser tunable in the telecommunications C-band. The suitability and potential of this technology for mass manufacture is demonstrated, with further opportunities for improvement detailed and discussed in the conclusion.

Development of germanium/silicon integration for near infrared detection

Silicon (Si) is the base material for electronic technologies and is emerging as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Applications for PICs are in the area of fibre-optic communication, biomedical devices, photovoltaics and imaging. Germanium (Ge), due to its suitable bandgap for telecommunications and its compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. There are two main approaches for Ge/Si integration: through epitaxial growth and through direct wafer bonding. The lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique which leads to a high density of dislocations while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in trap states which are expected to play a critical role. Understanding the physics of the interface is a key contribution of this thesis. This thesis investigates Ge/Si diodes using these two methods. The effects of interface traps on the static and dynamic performance of Ge/Si avalanche photodetectors have been modelled for the first time. The thesis outlines the original process development and characterization of mesa diodes which were fabricated by transferring a ~700 nm thick layer of p-type Ge onto n-type Si using direct wafer bonding and layer exfoliation. The effects of low temperature annealing on the device performance and on the conductivity of the interface have been investigated. It is shown that the diode ideality factor and the series resistance of the device are reduced after annealing. The carrier transport mechanism is shown to be dominated by generation–recombination before annealing and by direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing. The thesis presents a novel technique to realise photodetectors where one of the substrates is thinned by chemical mechanical polishing (CMP) after bonding the Si-Ge wafers. Based on this technique, Ge/Si detectors with remarkably high responsivities, in excess of 3.5 A/W at 1.55 μm at −2 V, under surface normal illumination have been measured. By performing electrical and optical measurements at various temperatures, the carrier transport through the hetero-interface is analysed by monitoring the Ge band bending from which a detailed band structure of the Ge/Si interface is proposed for the first time. The above unity responsivity of the detectors was explained by light induced potential barrier lowering at the interface. To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The wafer bonding approach followed by layer exfoliation or by CMP is a low temperature wafer scale process. In principle, the technique could be extended to other materials such as Ge on GaAs, or Ge on SOI. The unique results reported here are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout units in the form of 2D arrays of detectors. One potential future application is a low-cost Si process-compatible near infrared camera.

Análisis de la sensibilidad de distintos índices del ENSO para explicar los rendimientos de maíz en la región pampeana

p.53-60

La otra Ley de Foucault. Una lectura crítica

Few studies have addressed the relationship between law and power in the works of Michel Foucault. Some authors emphasize that law performs a completely secondary role in the diagram of power of modernity, while others argue that there is a close link between power relations and the law. Foucault's Law by Golden and Fitzpatrick aims to renew these discussions and reconstruct another law of Foucault. In this paper I make a critical reading of this work, highlighting the faulty presentation that the authors carried out of the works of Foucault.

Investigation of precision grinding process for production of silicon diaphragms

The application of precision grinding for the formation of a silicon diaphragm is investigated. The test structures involved 2-6 mm diam diaphragms with thicknesses in the range of 25-150 //m. When grinding is performed without supporting the diaphragm, bending occurs due to nonuniform removal of the silicon material over the diaphragm region. The magnitude of bending depends on the µNal thickness of the diaphragm. The results demonstrate that the use of a porous silicon support can significantly reduce the amount of bending, by a factor of up to 300 in the case of 50 m thick diaphragms. The use of silicon on insulator (SOI) technology can also suppress or eliminate bending although this may be a less economical process. Stress measurements in the diaphragms were performed using x-ray and Raman spectroscopies. The results show stress of the order of 1 X107-! X108 Pa in unsupported and supported by porous silicon diaphragms while SOI technology provides stress-free diaphragms. Results obtained from finite element method analysis to determine deterioration in the performance of a 6 mm diaphragm due to bending are presented. These results show a 10% reduction in performance for a 75 µm thick diaphragm with bending amplitude of 30 fim, but negligible reduction if the bending is reduced to

Comparative analysis of nanoscale MOS device architectures for RF applications

This paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical SOI MOSFETs. The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. The origin of higher parasitic capacitance in FinFETs, compared to planar MOSFETs is examined. RF figures of merit for planar and vertical MOS devices are compared, based on layout-area calculations.

Physical modelling of millimetre wave signal reflection from forward biased PIN diodes

This paper examines the DC power requirements of PIN diodes which, with suitable applied DC bias, have the potential to reflect or to permit transmission of millimetre wave energy through them by the process of inducing a semiconductor plasma layer in the i-region. The study is conducted using device level simulation of SOI and bulk PIN diodes and reflection modelling based on the Drude conduction model. We examined five diode lengths (60–140 µm) and seven diode thicknesses (4–100 µm). Simulation output for the diodes of varying thicknesses was subsequently used in reflection modelling to assess their performance for 100 GHz operation. It is shown that substantially high DC input power is required in order to induce near total reflection in SOI PIN diodes at 100 GHz. Thinner devices consume less DC power, but reflect less incident radiation for given input power. SOI diodes are shown to have improved carrier confinement compared with bulk diodes.

CMOS compatible RF MEMS switches with serpentine springs

This paper describes a serpentine flexure spring design and fabrication process development for radio frequency microelectromechanical (RF MEMS) capacitive switches with coplanar waveguide (CPW) lines. Sputtered tungsten is employed as the CPW line conductor instead of Au, a non-Si compatible material. The bridge membrane is fabricated from Al. The materials and fabrication process can be integrated with CMOS and SOI technology to reduce cost. Results show the MEMS switch has excellent performance with insertion loss 0.3dB, return loss -27dB at 30GHz and high isolation -30dB at 40GHz. The process developed promises to simplify the design and fabrication of RF MEMS on silicon.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.