Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Superjunction IGBT filling the gap between SJ MOSFET and ultrafast IGBT

In this letter, we report E off-versus-V ce tradeoff curves for vertical superjunction insulated-gate bipolar transistors (SJ IGBTs), exhibiting unusual inverse slopes dE off/dV ce > 0 in a transition region between purely unipolar and strongly bipolar device behaviors. This effect is due to the action of p-pillar hole current when depleting the drift layer of SJ IGBTs during turnoff and the impact of current gain on the transconductance. Such SJ IGBTs surpass by a very significant margin their superjunction MOSFET counterparts in terms of power-handling capability and on-state and turnoff losses, all at the same time. © 2012 IEEE.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.

全耗尽SOI MOSFET的制作及其辐射加固的研究

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

一种功率MOSFET驱动电路

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-06-04T08:36:34Z No. of bitstreams: 1 dspace.cfg: 33388 bytes, checksum: ac9630d3fdb36a155287a049e8b34eb7 (MD5)

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

功率MOSFET反向特性的分析模拟

对功率MOSFET的反向特性进行了模拟,着重分析了N沟功率MOSFET体内集成二极管的独特的作用,并对P沟器件在特性模拟时由于PSPICE模型参数的限制而表现出来的误差进行了分析,提出了改善措旋,并得到了与实际相符合的结论.

适合于PSPICE的一种精确的功率MOSFET等效电路

建立了一种新的功率MOSFET等效电路,以便利用先进的电路模拟软件PSPICE对功率MOSFET所有特性进行模拟和分析。对IR公司的各类HEXFET进行的模拟结果与其数据手册中的实验曲线十分吻合,表明该模型具有较高的精确性。