A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

Heteroepitaxial growth of novel SOI material Si/gamma-Al2O3/Si

In this paper, we report the fabrication of Si-based double hetero-epitaxial SOI materials Si/gamma-Al2O3/Si. First, single crystalline gamma-Al2O3 (100) insulator films were grown epitaxially on Si(100) by LPCVD, and then, Si(100) epitaxial films were grown on gamma-Al2O3 (100)/Si(100) epi-substrates using a CVD method similar to silicon on sapphire (SOS) epitaxial growth. The Si/gamma-Al2O3 (100)/Si(100) SOI materials are characterized in detail by RHEED, XRD and AES techniques. The results demonstrate that the device-quality novel SOI materials Si/gamma-Al2O3 (100)/Si(100) has been fabricated successfully and can be used for application of MOS device.

Studies of 6H-SiC devices

Silicon carbide (SiC) is recently receiving increased attention due to its unique electrical and thermal properties. It has been regarded as the most appropriate semiconductor material for high power, high frequency, high temperature, and radiation hard microelectronic devices. The fabrication processes and characterization of basic device on 6H-SiC were systematically studied. The main works are summarized as follows:The homoepitaxial growth on the commercially available single-crystal 6H-SiC wafers was performed in a modified gas source molecular beam epitaxy system. The mesa structured p(+)n junction diodes on the material were fabricated and characterized. The diodes showed a high breakdown voltage of 800 V at room temperature. They operated with good rectification characteristics from room temperature to 673 K.Using thermal evaporation, Ti/6H-SiC Schottky barrier diodes were fabricated. They showed good rectification characteristics from room temperature to 473 K. Using neon implantation to form the edge termination, the breakdown voltage was improved to be 800 V.n-Type 6H-SiC MOS capacitors were fabricated and characterized. Under the same growing conditions, the quality of polysilicon gate capacitors was better than Al. In addition, SiC MOS capacitors had good tolerance to gamma rays. (C) 2002 Published by Elsevier Science B.V.

微电子与光电子集成技术

微电子技术与光电子技术紧密结合，相互渗透，必将推进信息技术及相关的高新技术进入新的发展阶段。本书共分为9章，从技术基础和实际应用的角度出发，着重对微电子与光电子集成技术相关的工艺基础、基本原理和关键集成技术进行了详细阐述，主要内容包括光发射器件、光电探测器、光波导器件、光电子专用集成电路、硅基光电子集成回路、甚短距离光传输技术以及微电子与光电子混合集成技术等。 微电子与光电子集成技术的实用化进程，必将为21世纪科学技术的发展作出重大贡献。然而，微电子与光电子集成技术是信息技术发展的一个崭新方向，虽然各项关键技术的发展取得了一定的进步，但还存在诸多难题需要进一步解决和完善。 本书主要为从事集成光电子和光通信等相关技术研究的科研人员提供参考。

Recent progresses of SOI-based photonic devices - art. no. 60201R

SOI (Silicon on Insulator) based photonic devices, including stimulated emission from Si diode, RCE (Resonant Cavity Enhanced) photodiode with quantum structure, MOS (Metal Oxide Semiconductor) optical modulator with high frequency, SOI optical matrix switch and wavelength tunable filter are reviewed in the paper. The emphasis will be played on our recent results of SOI-based thermo-optic waveguide matrix switch with low insertion loss and fast response. A folding re-arrangeable non-blocking 4x4 matrix switch with total internal reflection (TIR) mirrors and a first blocking 16 x 16 matrix were fabricated on SOI wafer. The extinction ratio and the crosstalk are better. The insertion loss and the polarization dependent loss (PDL) at 1.55 mu m increase slightly with longer device length and more bend and intersecting waveguides. The insertion losses are expected to decrease 2-3 dB when anti-reflection films are added in the ends of the devices. The rise and fall times of the devices are 2.1 mu s and 2.3 mu s, respectively.

Recent progresses of silicon-based optoelectronic devices for application in fiber communication

Si-based optoelectronic devices, including stimulated emission from Si diode, 1.3 and 1.5mum SiGe photodetector with quantum structures, 1GHz MOS optical modulator, SOI optical switch matrix and wavelength tunable filter are reviewed in the paper.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.

ELECTRONIC-STRUCTURES OF THE ALKALI-CONTAINING BUCKMINSTERFULLERENES (A-DELTA-C60) (A=LI,NA,K,RB,CS) AND THE HALOGEN-CONTAINING BUCKMINSTERFULLERENES (H-DELTA-C60) (H=F,CL,BR,I)

The geometrical parameters and electronic structures of C60, (A partial derivative C60) (A = Li, Na, K, Rb, Cs) and (H partial derivative C60) (H = F, Cl, Br, I) have been calculated by the EHMO/ASED (atom superposition and electron delocalization) method. When putting a central atom into the C60 cage, the frontier and subfrontier orbitals of (A partial derivative C60) (A = Li, Na, K, Rb, Cs) and (H partial derivative C60) (H = F, Cl) relative to those of C60 undergo little change and thus, from the viewpoint of charge transfer, A (A = Li, Na, K, Rb, Cs) and H (H = F, Cl) are simply electron donors and acceptors for the C60 cage resPeCtively. Br is an electron acceptor but it does influence the frontier and subfrontier MOs for the C60 cage, and although there is no charge transfer between I and the C60 cage, the frontier and subfrontier MOs for the C60 cage are obviously influenced by I. The stabilities DELTAE(X) (DELTAE(X) = (E(X) + E(C60)) - E(x partial derivative C60)) follow the sequence I < Br < None < Cl < F < Li < Na < K < Rb < Cs while the cage radii r follow the inverse sequence. The stability order and the cage radii order have been explained by means of the (exp-6-1) potential.

THE DEPENDENCE OF THE INVERSION LAYER THICKNESS ON THE FILM THICKNESS IN THIN-FILM SOI STRUCTURES

The dependence of the inversion-layer thickness on the film thickness in thin-film SOI structure is analyzed theoretically by using computer simulation. A new concept and parameter, the critical thickness of thin film all-bulk inversion, is introduced for the design of thin-film MOS/SOI devices. It is necessary to select the film thickness T(s1) close to the all-bulk strong inversion critical thickness in order to get high-speed and high-power operation of ultra-thin film MOS/SOI devices.

A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.

A Numerical Method for Calculating Transmission Coefficients Across Arbitrary Potential Barriers with High Accuracy

We report a new method for calculating transmission coefficients across arbitrary potential barriers based on the Runge-Kutta method. A numerical solution of the Schrodinger equation is calculated using the Runge-Kutta method,and a new model is established to analyze the numerical results to find the transmission coefficient. This technique is applied to various cases, such as parabolic potential barrier and double-barrier structures. Transmission probability with high precision is obtained and discussed. The tunnelling current density through a MOS structure is also explored and the result coincides with the Fowler-Nordheim model,which indicates the applicability of our method.

SOI光波导高速电光调制器的研究进展

介绍了不同截面大小的SOI(silicon-on-insulator)波导单模条件,详细描述了几种降低传输损耗,消除偏振相关,提高耦合效率的技术手段.分析比较了一种带有MOS(metal-oxide-semiconductor)电容结构和一种具有微环结构的高速电光调制器,其调制频率分别达到10和1.5GHz.

Sensitivity of Total-Dose Radiation Hardness of SIMOX Buried Oxides to Doses of Nitrogen Implantation into Buried Oxides

In order to improve the total-dose radiation hardness of the buried oxides(BOX) in the structure of separa tion-by-implanted-oxygen(SIMOX) silicon-on-insulator(SOI), nitrogen ions are implanted into the buried oxides with two different doses,2 × 1015 and 3 × 1015 cm-2 , respectively. The experimental results show that the radiation hardness of the buried oxides is very sensitive to the doses of nitrogen implantation for a lower dose of irradiation with a Co-60 source. Despite the small difference between the doses of nitrogen implantation, the nitrogen-implanted 2 × 1015 cm-2 BOX has a much higher hardness than the control sample (i. e. the buried oxide without receiving nitrogen implantation) for a total-dose irradiation of 5 × 104rad(Si), whereas the nitrogen-implanted 3 × 1015 cm-2 BOX has a lower hardness than the control sample. However,this sensitivity of radiation hardness to the doses of nitrogen implantation reduces with the increasing total-dose of irradiation (from 5 × 104 to 5 × 105 rad (Si)). The radiation hardness of BOX is characterized by MOS high-frequency (HF) capacitance-voltage (C-V) technique after the top silicon layers are removed. In addition, the abnormal HF C-V curve of the metal-silicon-BOX-silicon(MSOS) structure is observed and explained.

部分耗尽型SOI CMOS模拟电路设计研究

介绍了部分耗尽型SOI MOS器件浮体状态下的Kink效应及对模拟电路的影响.阐述了4种常用体接触方式及其他消除部分耗尽型SOI MOS器件Kink效应的工艺方法,同时给出了部分耗尽型SOIMOSFET工作在浮体状态下时模拟电路的设计方法.

注氮工艺对SIMOX器件电特性的影响

研究了氮离子注入对SIMOX器件电特性的影响.氮注入SIMOX的埋氧层并退火后,将减小前栅MOS-FET/SIMOX的阈电压,提高其漏源击穿电压但对栅击穿电压影响较小.氮注入方式对SIMOX器件的I-V特性有重要影响.