Innovative Stereo Vision-Based Approach to Generate Dense Depth Map of Transportation Infrastructure

Three-dimensional (3-D) spatial data of a transportation infrastructure contain useful information for civil engineering applications, including as-built documentation, on-site safety enhancements, and progress monitoring. Several techniques have been developed for acquiring 3-D point coordinates of infrastructure, such as laser scanning. Although the method yields accurate results, the high device costs and human effort required render the process infeasible for generic applications in the construction industry. A quick and reliable approach, which is based on the principles of stereo vision, is proposed for generating a depth map of an infrastructure. Initially, two images are captured by two similar stereo cameras at the scene of the infrastructure. A Harris feature detector is used to extract feature points from the first view, and an innovative adaptive window-matching technique is used to compute feature point correspondences in the second view. A robust algorithm computes the nonfeature point correspondences. Thus, the correspondences of all the points in the scene are obtained. After all correspondences have been obtained, the geometric principles of stereo vision are used to generate a dense depth map of the scene. The proposed algorithm has been tested on several data sets, and results illustrate its potential for stereo correspondence and depth map generation.

Use of contexts in language model interpolation and adaptation

Language models (LMs) are often constructed by building multiple individual component models that are combined using context independent interpolation weights. By tuning these weights, using either perplexity or discriminative approaches, it is possible to adapt LMs to a particular task. This paper investigates the use of context dependent weighting in both interpolation and test-time adaptation of language models. Depending on the previous word contexts, a discrete history weighting function is used to adjust the contribution from each component model. As this dramatically increases the number of parameters to estimate, robust weight estimation schemes are required. Several approaches are described in this paper. The first approach is based on MAP estimation where interpolation weights of lower order contexts are used as smoothing priors. The second approach uses training data to ensure robust estimation of LM interpolation weights. This can also serve as a smoothing prior for MAP adaptation. A normalized perplexity metric is proposed to handle the bias of the standard perplexity criterion to corpus size. A range of schemes to combine weight information obtained from training data and test data hypotheses are also proposed to improve robustness during context dependent LM adaptation. In addition, a minimum Bayes' risk (MBR) based discriminative training scheme is also proposed. An efficient weighted finite state transducer (WFST) decoding algorithm for context dependent interpolation is also presented. The proposed technique was evaluated using a state-of-the-art Mandarin Chinese broadcast speech transcription task. Character error rate (CER) reductions up to 7.3 relative were obtained as well as consistent perplexity improvements. © 2012 Elsevier Ltd. All rights reserved.

A genetic map of large yellow croaker Pseudosciaena crocea

Genetic linkage maps were constructed for large yellow croaker Pseudosciaena crocea (Richardson, 1846) using AFLP and microsatellite markers in an F-1 family. Five hundred and twenty-three AFLP markers and 36 microsatellites were genotyped in the parents and 94 F-1 progeny. Among these, 362 AFLP markers and 13 SSR markers followed the 1:1 Mendelian segregation ratio (P > 0.05). The female genetic map contained 181 AFLP and 7 microsatellite markers forming 24 linkage groups spanning 2959.1 cM, while the male map consisted of 153 AFLP and 8 microsatellite markers in 23 linkage groups covering 2205.7 cM. One sex linked marker was mapped to the male map and co-segregated with the AFLP marker agacta355, suggesting an XY-male determination mechanism and this may be useful in the breeding of monosex populations. (c) 2007 Elsevier B.V. All rights reserved.

A Low-Voltage Silicon Light Emitting Device in Standard Salicide CMOS Technology

National Natural Science Foundation of China 60536030 60776024 60877035 90820002 National High-Technology Research and Development Program of China 2007AA04Z329 2007AA04Z254

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

Design of Low Power Multi-Standard Active-RC Filter for WLAN and DVB-H

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

A standard CMOS compatible monolithic photo-detector and trans-impedance amplifier

A 1GHz monolithic photo-detector (PD) and trans-impedance amplifier (TIA) is designed with the standard 0.35 mu m CMOS technique. The design of the photo-detector is analyzed and the CMOS trans-impedance amplifier is also analyzed in the paper. The integrating method is described too. The die photograph is also showed in the paper.

A silicon light emitting devices in standard CMOS technology

A silicon light emitting device is designed and simulated. It is fabricated in 0.6 mum standard CMOS technology. The device can give more than 1 muW optical power of visible light under reverse breakdown. The device can be turned on at a bias of 0.88 V and work in a large range of voltage: 1.0-6.0 V The external electrical-optical conversion efficiency is more than 10(-6). The optical spectrum of the device is between 540-650 nm, which have a clear peak near 580 nm. The emission mechanism can be explained by a hot carrier direct recombination model.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

Logistic Map耦合格子模型模拟环带

本论文采用Logistic Map耦合格子模型对高聚物中特有的环带球晶进行了模拟，所得到的模拟结果与实验结果吻合较好。同时，研究结果能够对实验制备环带球晶样品提供可靠的理论指导。 首先，我们对Logistic Map耦合格子模型及模型中的两个模拟参量μ和ε进行分析，同时结合实验中各种实验条件对聚合物结晶行为的影响，认为Logistic Map的动力学特征与聚合物结晶行为非常相似，并且参量μ与实验中的结晶温度相关，即随温度的升高而减小，而参量ε与实验中影响扩散的因素有关，即随温度的升高而增大、随分子量的增大而减小，并且随样品厚度的增大而增大。我们对模型的整个参数空间进行计算，得到了可以形成环带球晶形貌的参数范围，通过进一步研究发现环带图案的带宽随参量μ的增大而变窄，随参量ε的增大而变宽。上述研究结果与实验中带宽随实验条件的变化规律是一致的。 在得到环带图案的基础上，我们又进一步计算得到了靶状和螺旋状形貌的参量μ和ε的具体取值范围。通过改变μ和ε的参数取值，模拟了环带球晶形貌由靶状过渡到螺旋状的过程，即靶状图案的环带由外层向内层逐渐断裂成较短的条带结构，所有的条带结构呈现出以空间某处为中心团聚在一起的形貌；随后，这种“团聚”的形貌逐渐消失了，空间中小的条带结构的排列呈无序状态。随着参数的进一步变化，短的条带结构变成较长的带状结构，并且这些带状结构的边缘逐渐发生卷曲，最终形成了螺旋状图案。我们还考察了系统初值和耦合方式对上述图案的影响，结果发现，形成环带球晶的参数范围对系统初值没有明显的依赖性，然而靶状和螺旋状图案的分布受初值的影响较大。此外，发现只有采用交替耦合、并考虑长程耦合作用的Logistic Map耦合格子模型才可以得到环带球晶图案。 为了更好地与实验结果进行对比，我们利用Logistic Map耦合格子模型对二维空间中的几种受限体系进行了模拟。（一）对温度梯度场中的环带球晶进行模拟，发现环带球晶在低温处较易成核，向高温处生长，并且，高温处环带的带宽比低温处宽。（二）对格子宽度受限情况进行了模拟，发现随着受限方向的宽度越来越窄，球晶尺寸逐渐变小，相邻两个环带球晶碰撞产生的界线变短，三个相邻环带球晶所形成的界线的交汇点减少。（三）研究了受限边界上的成核作用对狭长格子中环带球晶的影响，结果发现，随着受限边界上成核点密度的不断增加，其形貌转变分为三个不同阶段：①当成核密度稍有增大时，环带球晶数量增加，直径变小；②继续增大边界成核密度，使得大量晶层从受限边界向格子内生长，导致环带球晶的数量减少，直径也减小；③当成核点增加到一定程度时，整个空间中只有极少数由格子内部成核生长且直径非常小的环带球晶，而占主导地位的是由成核点垂直于受限边界生长出的穿透晶层。这些模拟结果均与实验结果相符合。 我们将Logistic Map耦合映象格子模型发展到三维空间格子中，得到了与环带球晶形貌一致的图案，并且其带宽随模拟参量μ的增大而变窄，随ε的增大而变宽。这一规律性结果与二维正方格子的模拟结果是一致的。这一部分的研究结果还表明，边界条件和格子尺寸对模拟结果有显著的影响，周期性边界条件导致在小体积立方格子中只能得到靶状图案；而当格子尺寸很大时，可以得到螺旋状环带球晶的图案。最后，通过调节垂直于薄膜平面方向上的格子数来研究薄膜厚度对环带图案带宽的影响，发现环带的带宽随厚度的增加而变宽，这与实验中环带球晶的带宽随样品厚度的增加而变大的结论是一致的。

A linkage map of common carp (Cyprinus carpio) based on AFLP and microsatellite markers

P>Common carp (Cyprinus carpio) is an important fish for aquaculture, but genomics of this species is still in its infancy. In this study, a linkage map of common carp based on Amplified Fragment Length Polymorphism (AFLP) and microsatellite (SSR) markers has been generated using gynogenetic haploids. Of 926 markers genotyped, 151 (149 AFLPs, two SSRs) were distorted and eliminated from the linkage analyses. A total of 699 AFLP and 20 microsatellite (SSR) markers were assigned to the map, which comprised 64 linkage groups and covered 5506.9 cM Kosambi, with an average interval distance of 7.66 cM Kosambi. The normality tests on interval map distances showed a non-normal marker distribution. Visual inspection of the map distance distribution histogram showed a cluster of interval map distances on the left side of the chart, which suggested the occurrence of AFLP marker clusters. On the other hand, the lack of an obvious cluster on the right side showed that there were a few big gaps which need more markers to bridge. The correlation analysis showed a highly significant relatedness between the length of linkage group and the number of markers, indicating that the AFLP markers in this map were randomly distributed among different linkage groups. This study is helpful for research into the common carp genome and for further studies of genetics and marker-assisted breeding in this species.

A multi-standard active-RC filter with accurate tuning system

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architec-ture is presented. It exhibits 1EEE 802. 11a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 comer frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm~2 and 0.11 mm~2 (calibration circuit excluded), respectively.