Micromachined 300GHz high Q resonant slot frequency selective surface filter

The design of a low loss quasi-optical beam splitter which is required to provide efficient diplexing of the bands 316.5-325.5 GHz and 349.5-358.5 GHz is presented. To minimise the filter insertion loss, the chosen architecture is a three-layer freestanding array of dipole slot elements. Floquet modal analysis and finite element method computer models are used to establish the geometry of the periodic structure and to predict its spectral response. Two different micromachining approaches have been employed to fabricate close packed arrays of 460 mm long elements in the screens that form the basic building block of the 30mm diameter multilayer frequency selective surface. Comparisons between simulated and measured transmission coefficients for the individual dichroic surfaces are used to determine the accuracy of the computer models and to confirm the suitability of the fabrication methods.

High-performance 3D median filter architecture for medical image despeckling

A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

Multiplier-less realization of a poly-phase filter using LUT-based FPGAs

In DSP applications such as fixed transforms and filtering, the full flexibility of a general-purpose multiplier is not required and only a limited range of values is needed on one of the multiplier inputs. A new design technique has been developed for deriving multipliers that operate on a limited range of multiplicands. This can be used to produce FPGA implementations of DSP systems where area is dramatically improved. The paper describes the technique and its application to the design of a poly-phase filter on a Virtex FPGA. A 62% area reduction and 7% speed increase is gained when compared to an equivalent design using general purpose multipliers. It is also compared favourably to other known fixed coefficient approaches.