High sampling rate retimed DLMS filter implementations in Virtex-II FPGA

Autoria(s): Yi, Y.; Woods, Roger; Ting, L.K.; Cowan, Colin
Data(s)

01/10/2002
Identificador

http://pure.qub.ac.uk/portal/en/publications/high-sampling-rate-retimed-dlms-filter-implementations-in-virtexii-fpga(5e67d304-d289-441d-a6cd-030c18f0fae8).html
Idioma(s)

eng
Direitos

info:eu-repo/semantics/restrictedAccess
Fonte

Yi , Y , Woods , R , Ting , L K & Cowan , C 2002 , ' High sampling rate retimed DLMS filter implementations in Virtex-II FPGA ' Paper presented at IEEE Workshop on Signal Processing Systems (SIPS 02) , San Diego, California , United States , 01/10/2002 - 01/10/2002 , pp. 139-145 .
Tipo

conferenceObject
Acesso ao item digital