Doping during low-temperature growth of materials for n-p-n Si/SiGe/Si heterojuction bipolar transistor by gas source molecular beam epitaxy

In situ doping for growth of n-p-n Si/SiGe/Si heterojuction bipolar transistor (HBT) structural materials in Si gas source molecular beam epitaxy is investigated. We studied high n-type doping kinetics in Si growth using disilane and phosphine, and p-type doping in SiGe growth using disilane, soild-Ge, and diborane with an emphasis on the effect of Ge on B incorporation. Based on these results, in situ growth of n-p-n Si/SiGe/Si HBT device structure is demonstrated with designed structural and carrier profiles, as verified from characterizations by X-ray diffraction, and spreading resistance profiling analysis. (C) 2000 Elsevier Science B.V. All rights reserved.

Growth and characterization of InGaAs/InAlAs/InP high-electron-mobility transistor structures towards high channel conductivity

High-quality InGaAs/InAlAs/InP high-electron-mobility transistor (HEMT) structures with lattice-matched or pseudomorphic channels have been grown by molecular-beam epitaxy (MBE). The purpose of this work is to enhance the channel conductivity by changing the epitaxial structure and growth process. With the use of pseudomorphic step quantum-well channel, the highest channel conductivity is achieved at x = 0.7, the corresponding electron mobilities are as high as 12300 (300 K) and 61000 cm(2)/V.s (77 K) with two-dimensional electron gas (2DEG) density of 3.3 x 10(12) cm(-2). These structures are comprehensively characterized by Hall measurements, photoluminescence, double crystal X-ray diffraction and transmission electron microscopy. Strong room-temperature luminescence is observed, demonstrating the high optical quality of the samples. We also show that decreasing the In composition in the InyAl1-yAs spacer is very effective to increase the 2DEG density of PHEMT structures. (C) 1998 Published by Elsevier Science B.V. All rights reserved.

Mode analysis of photonic crystal polarization beam splitter and its application in integrated circuits design - art. no. 698437

In this work, the guided modes of a photonic crystal polarization beam splitter (PC-PBS) are studied. We demonstrate that the transmission of a low-loss photonic crystal 120 degrees waveguide bend integrated with the PBS will be influenced if the PBS is multi-moded. We propose a single-moded PC-PBS structure by introducing deformed structures, and it shows twice the enhancement of the transmission. This device with remarkable improvement of performance is promising in the use of photonic crystal integrated circuits design.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

Effect of the implantation of fluorine on the mobility of channel electron for partially depleted SOI nMOSFET

The mobility of channel electron, for partially depleted Sol nMOSFET in this paper, decreases with the increase of implanted fluorine dose in buried oxide layer. But, the experimental results also show that it is larger for the transistor corresponding to the lowest implantation dose than no implanted fluorine in buried layer. It is explained in tern-is of a "lubricant" model. Mien fluorine atoms are implanted in the top silicon layer, the mobility is the largest. In addition, a positive shift of threshold voltage has also been observed for the transistors fabricated on the Sol wafers processed by the implantation of fluorine. The causes of all the above results are discussed.

An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

Self-consistent analysis of AlSb/InAs high electron mobility transistor structures

The influences of channel layer width, spacer layer width, and delta-doping density on the electron density and its distribution in the AlSb/InAs high electron mobility transistors (HEMTs) have been studied based on the self-consistent calculation of the Schrodinger and Poisson equations with both the strain and nonparabolicity effects being taken into account. The results show that, having little influence on the total two dimensional electron gas (2DEG) concentration in the channel, the HEMT's channel layer width has some influence on the electron mobility, with a channel as narrow as 100-130 angstrom being more beneficial. For the AlSb/InAs HEMT with a Te delta-doped layer, the 2DEG concentration as high as 9.1 X 10(12) cm(-2) can be achieved in the channel by enhancing the delta-doping concentration without the occurrence of the parallel conduction. When utilizing a Si delta-doped InAs layer as the electron-supplying layer of the AlSb/InAs HEMT, the effect of the InAs donor layer thickness is studied on the 2DEG concentration. To obtain a higher 2DEG concentration in the channel, it is necessary to use an InAs donor layer as thin as 4 monolayer. To test the validity of our calculation, we have compared our theoretical results (2DEG concentration and its distribution in different sub-bands of the channel) with the experimental ones done by other groups and show that our theoretical calculation is consistent with the experimental results.

IMPROVEMENT OF STRUCTURAL INSTABILITY OF THE ION-SENSITIVE FIELD-EFFECT TRANSISTOR (ISFET)

Three causes involved in the instability of the ISFET are proposed in this study. First, it is ascertained that hydroxyl group resident at the surface of the Si3N4 film or in the electrolyte solution is most active and subject to gain or loss of electrons. This is one of the main causes for ISFET structural instability. Secondly, the stability of the pH-sensitive FET varies with deposition conditions in the fabrication process of the ISFET. This proves to be another cause of ISFET instability. Thirdly, the pH of the measured solution varies with the measuring process and time, contributing to the instability, but is not a cause of the instability of the pH-ISFET itself. We utilized the technique of readjusting and controlling the ratio of hydroxyl groups to amine groups to enhance the stability of the ISFET. Our techniques to improve stability characteristics proved to be effective in practice.

Detection of Terahertz Photon by GaAs-Based Single Electron Transistor at Low Temperatures

A reproducible terahertz (THz) photocurrent was observed at low temperatures in a Schottky wrap gate single electron transistor with a normal-incident of a CH_3OH gas laser with the frequency 2. 54THz.The change of source-drain current induced by THz photons shows that a satellite peak is generated beside the resonance peak. THz photon energy can be characterized by the difference of gate voltage positions between the resonance peak and satellite peak. This indicates that the satellite peak exactly results from the THz photon-assisted tunneling. Both experimental results and theoretical analysis show that a narrow spacing of double barriers is more effective for the enhancement of THz response.

A Multi-Finger Si_(1-x)Ge_x/Si Heterojunction Bipolar Transistor for Wireless Power Amplifier Applications

A large area multi-finger configuration power SiGe HBT device(with an emitter area of about 880μm~2)was fabricated with 2μm double-mesa technology.The maximum DC current gain β is 214.The BV_(CEO) is up to 10V,and the BV_(CBO) is up to 16V with a collector doping concentration of 1×10~(17)cm~(-3) and collector thickness of 400nm.The device exhibits a maximum oscillation frequency f_(max) of 19.3GHz and a cut-off frequency f_T of 18.0GHz at a DC bias point of I_C=30mA and V_(CE)=3V.MSG(maximum stable gain)is 24.5dB,and U(Mason unilateral gain)is 26.6dB at 1GHz.Due to the novel distribution layout,no notable current gain fall-off or thermal effects are observed in the I-V characteristics at high collector current.