Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT

Autoria(s): Victor Khomenko; Maciej Koutny; Alex Yakovlev
Data(s)

2005
Identificador

http://ir.iscas.ac.cn/handle/311060/1220

http://www.irgrid.ac.cn/handle/1471x/66357
Idioma(s)

中文
Fonte

Victor Khomenko,Maciej Koutny,Alex Yakovlev.Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT.Fundamenta Informaticae,2005,70(1):49 - 73
Tipo

期刊论文
Acesso ao item digital