SOI集成光电子器件

Silicon-on-insulator (SOI)集成光电子器件的工艺与标准CMOS工艺完全兼容，采用SOI技术可以实现低成本的整片集成光电子回路。文章回顾了近几年来SOI集成光电子器件的发展以及一些最新的研究进展。

非对称全内反射型SOI波导开关器件模型分析

根据有效折射率法和光束传播法分析了大截面单模SOI脊形X型交叉波导的传输特性.指出交叉角在1.5-2°内,因导波模式引起耦合作用而导致的串音小于-25dB;采用波动光学原理分析了非对称全内反射开关导模的传输和反射特性;讨论了等离子体色散效应,pn结大注入效应以及Goos-Hanchken位移,并分析了非对我全内反射型SOI光波导开关的电学性质.据此优化设计了该器件的结构参数和电学参数.

利用能量过滤成像技术对注氮SOI的研究

于2010-11-23批量导入

MMI optical couplers and switches with SOI technology

MMI (multimode interference) coupler, modulator and switch based on SOI (silicon- on-insulator) have been become more and more attractive in optical systems since they show important performances. SiO2 thin cladding layers (<1.0mum) can be used in SOI waveguide due to the large index step between Si and SiO2, making them compatible with the VLSI technology. The design and fabrication of multimode interference (MMI) optical coupler, modulator and switche in SOI technology are presented in the paper. The results demonstrated that the modulator has an extinction ratio of -11.0dB and excess loss of -2.5dB, while the optical switch has a crosstalk of -12.5dB and responding time of less than 20 mus.

Heteroepitaxial growth of novel SOI material Si/gamma-Al2O3/Si

In this paper, we report the fabrication of Si-based double hetero-epitaxial SOI materials Si/gamma-Al2O3/Si. First, single crystalline gamma-Al2O3 (100) insulator films were grown epitaxially on Si(100) by LPCVD, and then, Si(100) epitaxial films were grown on gamma-Al2O3 (100)/Si(100) epi-substrates using a CVD method similar to silicon on sapphire (SOS) epitaxial growth. The Si/gamma-Al2O3 (100)/Si(100) SOI materials are characterized in detail by RHEED, XRD and AES techniques. The results demonstrate that the device-quality novel SOI materials Si/gamma-Al2O3 (100)/Si(100) has been fabricated successfully and can be used for application of MOS device.

Experimental study on heavy ion single event effects in SOI SRAMs

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened military and space applications. The use of SOI has been motivated by the full dielectric isolation of individual transistors, which prevents latch-up. The sensitive region for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single event upset (SEU). In this study, 64 kB SOI SRAMs were exposed to different heavy ions, such as Cu, Br, I, Kr. Experimental results show that the heavy ion SEU threshold linear energy transfer (LET) in the 64 kB SOI SRAMs is about 71.8 MeV cm(2)/mg. Accorded to the experimental results, the single event upset rate (SEUR) in space orbits were calculated and they are at the order of 10(-13) upset/(day bit).

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Discriminations à l’emploi à l’égard des personnes LGBT et estime de soi

info:eu-repo/semantics/nonPublished