Error probability in synchronous digital circuits due to power supply noise

This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits.The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recoveringtechniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.

Via-configurable transistor array: a regular design technique to improve ICs yield

Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That iswhy regular techniques with different degrees of regularity are emerging as possible solutions. Our proposal is a new regular layout design technique called Via-Configurable Transistors Array (VCTA) that pushes to the limit circuit layout regularity for devices and interconnects in order to maximize regularity benefits. VCTA is predicted to perform worse than the Standard Cell approach designs for a certain technology node but it will allow the use of a future technology on an earlier time. Ourobjective is to optimize VCTA for it to be comparable to the Standard Cell design in an older technology. Simulations for the first unoptimized version of our VCTA of delay and energy consumption for a Full Adder circuit in the 90 nm technology node are presented and also the extrapolation for Carry-RippleAdders from 4 bits to 64 bits.

Desplegament dels circuits dedicats de 1 i 10 Gbps entre el PIC i el CERN

Aquest projecte consisteix a realitzar el disseny i desplegament d'una connexió entre el Port d'Informació Científica (PIC) i el Consell Europeu per a la Recerca Nuclear (CERN) sobre un circuit dedicat amb una velocitat de transferència de 10 Gbps. En una primera fase el desplegament de la connexió es realitza sobre un circuit dedicat de 1 Gbps. El projecte implica la certificació dels circuits dedicats de 1 i 10 Gbps i el disseny dels plans d'actuació que han de permetre la integració de les noves connexions dins la xarxa i els serveis del PIC.

Caracterització d'oscil·ladors basats en CMOS-M/NEMS i la seva aplicació com a sensors de massa

El present projecte tracta sobre la caracterització d'oscil·ladors basats en ressonadors micro/nanoelectromecànics (M/NEMS) i la seva aplicació com a sensors de massa. Els oscil·ladors utilitzats es basen en un pont i una palanca ressoants M/NEMS, integrats en tecnologia CMOS. En primer lloc s'ha fet una introducció teòrica als conceptes utilitzats per a entendre el funcionament i la caracterització dels dispositius. A continuació s'han realitzat proves per tal de caracteritzar els paràmetres importants per a l'ús dels oscil·ladors com a sensors de massa, com la seva estabilitat en freqüència. Per acabar s'han aplicat aquests sensors en la caracterització i modelització del flux de massa a través d'obertures de dimensions micromètriques.

Cortical mapping of the neuronal circuits modulating the muscle tone. Introduction to the electrophysiological treatment of the spastic hand.

L’objectiu d’aquest estudi es investigar l’organització cortical junt amb la connectivitat còrtico-subcortical en subjectes sans, com a estudi preliminar. Els mapes corticals s’han fet per TMS navegada, i els punts motors obtinguts s’han exportant per estudi tractogràfic i anàlisi de las seves connexions. El coneixement precís de la localització de l’àrea cortical motora primària i les seves connexions es la base per ser utilitzada en estudis posteriors de la reorganització cortical i sub-cortical en pacients amb infart cerebral. Aquesta reorganització es deguda a la neuroplasticitat i pot ser influenciada per els efectes neuromoduladors de la estimulació cerebral no invasiva.

Real-Time implementation of a blind authentication method using self-synchronous speech watermarking

A blind speech watermarking scheme that meets hard real-time deadlines is presented and implemented. In addition, one of the key issues in these block-oriented watermarking techniques is to preserve the synchronization. Namely, to recover the exact position of each block in the mark extract process. In fact, the presented scheme can be split up into two distinguished parts, the synchronization and the information mark methods. The former is embedded into the time domain and it is fast enough to be run meeting real-time requirements. The latter contains the authentication information and it is embedded into the wavelet domain. The synchronization and information mark techniques are both tunable in order to allow a con gurable method. Thus, capacity, transparency and robustness can be con gured depending on the needs. It makes the scheme useful for professional applications, such telephony authentication or even sending information throw radio applications.

Non-invasive RF built-in testing using on-chip temperature sensors

This poster shows how to efficiently observe high-frequency figures of merit in RF circuits by measuring DC temperature with CMOS-compatible built-in sensors.

A gated single-photon avalanche diode array fabricated in a conventional CMOS process for triggered systems

A bidimensional array based on single-photon avalanche diodes for triggered imaging systems is presented. The diodes are operated in the gated mode of acquisition to reduce the probability to detect noise counts interfering with photon arrival events. In addition, low reverse bias overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process gets rid of afterpulses and offers a reduced dark count probability by applying the proposed modes of operation. The detector exhibits a dynamic range of 15 bits with short gated"on" periods of 10ns and a reverse bias overvoltage of 1.0V.

Avoiding sensor blindness in Geiger mode avalanche photodiode arrays fabricated in a conventional CMOS process

The need to move forward in the knowledge of the subatomic world has stimulated the development of new particle colliders. However, the objectives of the next generation of colliders sets unprecedented challenges to the detector performance. The purpose of this contribution is to present a bidimensional array based on avalanche photodiodes operated in the Geiger mode to track high energy particles in future linear colliders. The bidimensional array can function in a gated mode to reduce the probability to detect noise counts interfering with real events. Low reverse overvoltages are used to lessen the dark count rate. Experimental results demonstrate that the prototype fabricated with a standard HV-CMOS process presents an increased efficiency and avoids sensor blindness by applying the proposed techniques.

Continuous phase shift of sinusoidal signals using injection locked oscillators

This work presents an alternative to generate continuous phase shift of sinusoidal signals based on the use of super harmonic injection locked oscillators (ILO). The proposed circuit is a second harmonic ILO with varactor diodes as tuning elements. In the locking state, by changing the varactor bias, a phase shift instead of a frequency shift is observed at the oscillator output. By combining two of these circuits, relative phases up to 90 could be achieved. Two prototypes of the circuit have been implemented and tested, a hybrid version working in the range of 200-300 MHz and a multichip module (MCM) version covering the 900¿1000 MHz band.

A current-mode interface circuit for a piezoresistive pressure sensor

An interfacing circuit for piezoresistive pressure sensors based on CMOS current conveyors is presented. The main advantages of the proposed interfacing circuit include the use of a single piezoresistor, the capability of offset compensation, and a versatile current-mode configuration, with current output and current or voltage input. Experimental tests confirm linear relation of output voltage versus piezoresistance variation.

Pulse propagation sustained by noise in arrays of bistable electronic circuits

One-dimensional arrays of nonlinear electronic circuits are shown to support propagation of pulses when operating in a locally bistable regime, provided the circuits are under the influence of a global noise. These external random fluctuations are applied to the parameter that controls the transition between bistable and monostable dynamics in the individual circuits. As a result, propagating fronts become destabilized in the presence of noise, and the system self-organizes to allow the transmission of pulses. The phenomenon is also observed in weakly coupled arrays, when propagation failure arises in the absence of noise.