Hydrogel-Forming Microneedle Arrays for Enhanced Transdermal Drug Delivery

Unique microneedle arrays prepared from crosslinked polymers, which contain no drug themselves, are described. They rapidly take up skin interstitial fluid upon skin insertion to form continuous, unblockable, hydrogel conduits from attached patch-type drug reservoirs to the dermal microcirculation. Importantly, such microneedles, which can be fabricated in a wide range of patch sizes and microneedle geometries, can be easily sterilized, resist hole closure while in place, and are removed completely intact from the skin. Delivery of macromolecules is no longer limited to what can be loaded into the microneedles themselves and transdermal drug delivery is now controlled by the crosslink density of the hydrogel system rather than the stratum corneum, while electrically modulated delivery is also a unique feature. This technology has the potential to overcome the limitations of conventional microneedle designs and greatly increase the range of the type of drug that is deliverable transdermally, with ensuing benefits for industry, healthcare providers and, ultimately, patients.

Allele resolution of HLA-A using oligonucleotide probes in a two-stage typing strategy

High-resolution polymerase chain reaction using sequence-specific oligonucleotide probes (PCR-SSOP) typing methods for HLA-A identification have been established. The four systems, which operate independently of each other, are intended for use as secondary typing systems following HLA-A identification with a medium-resolution PCR-SSOP technique. The systems, all using digoxigenin-labelled probes, are based on group specific amplifications for resolution of: i) HLA-A*29 & -A*33; ii) HLA-A*24 & -A*30; and iii) HLA-A*26, -A*25, -A*11, -A*34, -A*66 and -A*68 alleles, respectively. The fourth system, for the detection of HLA-A*02 alleles, is a modification of a previously reported PCR-SSOP subtyping system. The methods have been applied to individuals from the local bone marrow registry and HLA-A allele frequencies for the Northern Ireland population have been established.

Localization of erythropoietin gene expression in proximal renal tubular cells detected by digoxigenin-labelled oligonucleotide probes

Erythropoietin (EPO) is the main humoral stimulus of erythropoiesis. In adult mammals, the kidney releases EPO in response to hypoxic stress. Conflicting data have suggested either renal tubular or peritubular cell origins of EPO synthesis in vivo. In situ hybridization studies were performed to define further the kidney cell type(s) capable of increasing EPO gene expression during hypoxic stimulation. EPO gene expression was stimulated in mice exposed to acute hypobaric hypoxia. Kidneys from hypoxic and control normoxic mice were obtained. Six digoxigenin-labelled oligonucleotide probes complementary to EPO exon sequences were utilized for in situ hybridization for EPO messenger RNA. Positive hybridization signals were identified in some proximal tubular cells, confined to the inner third of the renal cortex of hypoxic mouse kidney.

Strong Coupling and Long-Range Collective Interactions in Optomechanical Arrays

We investigate the collective optomechanics of an ensemble of scatterers inside a Fabry-Pérot resonator and identify an optimized configuration where the ensemble is transmissive, in contrast to the usual reflective optomechanics approach. In this configuration, the optomechanical coupling of a specific collective mechanical mode can be several orders of magnitude larger than the single-element case, and long-range interactions can be generated between the different elements since light permeates throughout the array. This new regime should realistically allow for achieving strong single-photon optomechanical coupling with massive resonators, realizing hybrid quantum interfaces, and exploiting collective long-range interactions in arrays of atoms or mechanical oscillators.

From bit level systolic arrays to HDTV processor chips

The initial part of this paper reviews the early challenges (c 1980) in achieving real-time silicon implementations of DSP computations. In particular, it discusses research on application specific architectures, including bit level systolic circuits that led to important advances in achieving the DSP performance levels then required. These were many orders of magnitude greater than those achievable using programmable (including early DSP) processors, and were demonstrated through the design of commercial digital correlator and digital filter chips. As is discussed, an important challenge was the application of these concepts to recursive computations as occur, for example, in Infinite Impulse Response (IIR) filters. An important breakthrough was to show how fine grained pipelining can be used if arithmetic is performed most significant bit (msb) first. This can be achieved using redundant number systems, including carry-save arithmetic. This research and its practical benefits were again demonstrated through a number of novel IIR filter chip designs which at the time, exhibited performance much greater than previous solutions. The architectural insights gained coupled with the regular nature of many DSP and video processing computations also provided the foundation for new methods for the rapid design and synthesis of complex DSP System-on-Chip (SoC), Intellectual Property (IP) cores. This included the creation of a wide portfolio of commercial SoC video compression cores (MPEG2, MPEG4, H.264) for very high performance applications ranging from cell phones to High Definition TV (HDTV). The work provided the foundation for systematic methodologies, tools and design flows including high-level design optimizations based on "algorithmic engineering" and also led to the creation of the Abhainn tool environment for the design of complex heterogeneous DSP platforms comprising processors and multiple FPGAs. The paper concludes with a discussion of the problems faced by designers in developing complex DSP systems using current SoC technology. © 2007 Springer Science+Business Media, LLC.

IMPLEMENTATION OF SIGNAL PROCESSING FUNCTIONS USING 1-BIT SYSTOLIC ARRAYS.

The use of systolic arrays of 1-bit cells to implement a range of important signal processing functions is demonstrated. Two examples, a pipelined multiplier and a pipelined bit-slice transform circuit, are given. This approach has many important implications for silicon technology, and these are outlined.

UTILISATION OF BIT LEVEL SYSTOLIC ARRAYS IN WORD LEVEL SYSTEMS.

Bit level systolic array structures for computing sums of products are studied in detail. It is shown that these can be sub-divided into two classes and that, within each class, architectures can be described in terms of a set of constraint equations. It is further demonstrated that high performance system level functions with attractive VLSI properties can be constructed by matching data flow geometries in bit level and word level architectures.

MAPPING SYSTEM LEVEL FUNCTIONS ON TO BIT LEVEL SYSTOLIC ARRAYS.

Bit-level systolic-array structures for computing sums of products are studied in detail. It is shown that these can be subdivided into two classes and that within each class architectures can be described in terms of a set of constraint equations. It is further demonstrated that high-performance system-level functions with attractive VLSI properties can be constructed by matching data-flow geometries in bit-level and word-level architectures.

BIT-LEVEL SYSTOLIC ARRAYS.

A systolic array is an array of individual processing cells each of which has some local memory and is connected only to its nearest neighbours in the form of a regular lattice. On each cycle of a simple clock every cell receives data from its neighbouring cells and performs a specific processing operation on it. The resulting data is stored within the cell and passed on to neighbouring cells on the next clock cycle. This paper gives an overview of work to date and illustrates the application of bit-level systolic arrays by means of two examples: (1) a pipelined bit-slice circuit for computing matrix x vector transforms; and (2) a bit serial structure for multi-bit convolution.

RELATIONSHIP BETWEEN WORD AND BIT LEVEL SYSTOLIC ARRAYS AS APPLIED TO MATRIX multiplied by MATRIX MULTIPLICATIONS.

The mapping of matrix multiplied by matrix multiplication onto both word and bit level systolic arrays has been investigated. It has been found that well defined word and bit level data flow constraints must be satisfied within such circuits. An efficient and highly regular bit level array has been generated by exploiting the basic compatibilities in data flow symmetries at each level of the problem. A description of the circuit which emerges is given and some details relating to its practical implementation are discussed.

Use of data dependence graphs in the design of bit-level systolic arrays

The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply using the dependence graph and cut-set procedure developed by S. Y. Kung (1988). This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique can be applied to ripple-through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design.

VQ tree search system based on bit level systolic arrays

A bit-level systolic array system for performing a binary tree vector quantization (VQ) codebook search is described. This is based on a highly regular VLSI building block circuit. The system in question exhibits a very high data rate suitable for a range of real-time applications. A technique is described which reduces the storage requirements of such a system by 50%, with a corresponding decrease in hardware complexity.

BIT-LEVEL SYSTOLIC ARRAYS FOR SIGNAL AND IMAGE PROCESSING.

This paper describes the design and the architecture of a bit-level systolic array processor. The bit-level systolic array described is directly applicable to a wide range of image processing operations where high performance and throughput are essential. The architecture is illustrated by describing the operation of the correlator and convolver chips which are being developed. The advantage of the system is also discussed.

Bit-level systolic arrays for IIR filtering.

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.