Use of data dependence graphs in the design of bit-level systolic arrays
Data(s) |
01/05/1990
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Resumo |
The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply using the dependence graph and cut-set procedure developed by S. Y. Kung (1988). This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique can be applied to ripple-through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design. |
Identificador | |
Idioma(s) |
eng |
Direitos |
info:eu-repo/semantics/restrictedAccess |
Fonte |
McCanny , J V , McWhirter , J G & Kung , S-Y 1990 , ' Use of data dependence graphs in the design of bit-level systolic arrays ' IEEE Transactions on Acoustics, Speech, and Signal Processing , vol 38 , no. 5 , pp. 787-793 . DOI: 10.1109/29.56023 |
Tipo |
article |