CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP.

The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.

Programmable image processing chip

A new high performance, programmable image processing chip targeted at video and HDTV applications is described. This was initially developed for image small object recognition but has much broader functional application including 1D and 2D FIR filtering as well as neural network computation. The core of the circuit is made up of an array of twenty one multiplication-accumulation cells based on systolic architecture. Devices can be cascaded to increase the order of the filter both vertically and horizontally. The chip has been fabricated in a 0.6 µ, low power CMOS technology and operates on 10 bit input data at over 54 Megasamples per second. The introduction gives some background to the chip design and highlights that there are few other comparable devices. Section 2 gives a brief introduction to small object detection. The chip architecture and the chip design will be described in detail in the later sections.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Wavelet packet transforms for system-on-chip applications

A methodology for the production of silicon cores for wavelet packet decomposition has been developed. The scheme utilizes efficient scalable architectures for both orthonormal and biorthogonal wavelet transforms. The cores produced from these architectures can be readily scaled for any wavelet function and are easily configurable for any subband structure. The cores are fully parameterized in terms of wavelet choice and appropriate wordlengths. Designs produced are portable across a range of silicon foundries as well as FPGA and PLD technologies. A number of exemplar implementations have been produced.

Programmable high-performance IIR filter chip

The paper presents a state-of-the-art commercial demonstrator chip for infinite impulse response (IIR) filtering. The programmable IIR filter chip contains eight multiplier/accumulators that can be configured in one of five different modes to implement up to a 16th-order IIR filter. The multiply-accumulate block is based on a highly regular systolic array architecture and uses a redundant number system to overcome problems of pipelining in the feedback loop. The chip has been designed using the GEC Plessey Semiconductors CLA 78000 series gate array, operates on 16-bit two's complement data and has a clock speed of 30 MHz. Issues such as overflow detection and design for testability have also been addressed and are described.

Design of interlock-free combined allocators for Networks-on-Chip

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA.

Assessment of a multiplexing high throughput immunochemical SPR biosensor in measuring multiple proteins on a single biosensor chip

Multiplexed immunochemical detection platforms offer the potential to decrease labour demands, increase sample throughput and decrease overall time to result. A prototype four channel multiplexed high throughput surface plasmon resonance biosensor was previously developed, for the detection of food related contaminants. A study focused on determining the instruments performance characteristics was undertaken. This was followed by the development of a multiplexed assay for four high molecular weight proteins. The protein levels were simultaneously evaluated in serum samples of 10-week-old veal calves (n = 24) using multiple sample preparation methods. Each of the biosensor's four channels were shown to be independent of one another and produced multiplexed within run repeatability (n = 6) ranging from 2.0 to 6.7%CV, for the four tested proteins, whilst between run reproducibility (n = 4) ranged from 1.5 to 8.9%CV. Four calibration curves were successfully constructed before serum sample preparation was optimised for each protein. Multiplexed concentration analysis was successfully performed on four channels revealing that each proteins concentration was consistent across the twenty-four tested animals. Signal reproducibility (n > 19) on a further long term study revealed coefficient of variation ranging from 1.1% to 7.3% and showed that the multiplexed assay was stable for at least 480 cycles. These findings indicate that the performance characteristics fall within the range of previously published data for singleplex optical biosensors and that the multiplexing biosensor is fit-for-purpose for simultaneous concentration analysis in many different types of applications such as the multiplexed detection of markers of growth-promoter abuse and multiplexed detection of residues of concern in food safety. © 2013 Elsevier B.V.

A Trip from a Tube to a Chip Applied Micro and Nanotechnology in Biotechnology, Veterinary and Life Sciences

More than 200 known diseases are transmitted via foods or food products. In the United States, food-borne diseases are responsible for 76 million cases of illness, 32,500 cases of hospitalisation and 5000 cases of death yearly. The ongoing increase in worldwide trade in livestock, food, and food products in combination with increase in human mobility (business- and leisure travel, emigration etc.) will increase the risk of emergence and spreading of such pathogens. There is therefore an urgent need for development of rapid, efficient and reliable methods for detection and identification of such pathogens.

Microchipfabrication has had a major impact on electronics and is expected to have an equally pronounced effect on life sciences. By combining micro-fluidics with micromechanics, micro-optics, and microelectronics, systems can be realized to perform complete chemical or biochemical analyses. These socalled ’Lab-on-a-Chip’ will completely change the face of laboratories in the future where smaller, fully automated devices will be able to perform assays faster, more accurately, and at a lower cost than equipment of today. A general introduction of food safety and applied micro-nanotechnology in life sciences will be given. In addition, examples of DNA micro arrays, micro fabricated integrated PCR chips and total integrated lab-on-achip systems from different National and EU research projects being carried out at the Laboratory of Applied Micro- Nanotechnology (LAMINATE) group at the National Veterinary Institute (DTU-Vet) Technical University of Denmark and the BioLabchip group at the Department of Micro and Nanotechnology (DTU-Nanotech), Technical University of Denmark (DTU), Ikerlan-IK4 (Spain) and other 16 partners from different European countries will be presented.

GELIFICATION - A SIMPLE AND EFFICIENT METHOD FOR ON-CHIP STORAGE OF REAGENTS: TOWARDS LAB-ON-A-CHIP SYSTEMS FOR POINT-OF-CARE DIAGNOSTICS

In this study, we describe a simple and efficient method for on-chip storage of reagents for point-of-care (POC) diagnostics. The method is based on gelification of all reagents required for on-chip PCR-based diagnostics as a ready-to-use product. The result reported here is a key step towards the development of a ready and easy to use fully integrated Lab-on-a-chip (LOC) system for fast, cost-effective and efficient POC diagnostics analysis.