95 resultados para radial birefringent filter


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The design of a low loss quasi-optical beam splitter which is required to provide efficient diplexing of the bands 316.5-325.5 GHz and 349.5-358.5 GHz is presented. To minimise the filter insertion loss, the chosen architecture is a three-layer freestanding array of dipole slot elements. Floquet modal analysis and finite element method computer models are used to establish the geometry of the periodic structure and to predict its spectral response. Two different micromachining approaches have been employed to fabricate close packed arrays of 460 mm long elements in the screens that form the basic building block of the 30mm diameter multilayer frequency selective surface. Comparisons between simulated and measured transmission coefficients for the individual dichroic surfaces are used to determine the accuracy of the computer models and to confirm the suitability of the fabrication methods.

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This paper examines the relative efficiency of UK credit unions. Radial and non-radial measures of input cost efficiency plus associated scale efficiency measures are computed for a selection of input output specifications. Both measures highlighted that UK credit unions have considerable scope for efficiency gains. It was mooted that the documented high levels of inefficiency may be indicative of the fact that credit unions, based on clearly defined and non-overlapping common bonds, are not in competition with each other for market share. Credit unions were also highlighted as suffering from a considerable degree of scale inefficiency with the majority of scale inefficient credit unions subject to decreasing returns to scale. The latter aspect highlights that the UK Government's goal of larger credit unions must be accompanied by greater regulatory freedom if inefficiency is to be avoided. One of the advantages of computing non-radial measures is that an insight into potential over- or under-expenditure on specific inputs can be obtained through a comparison of the non-radial measure of efficiency with the associated radial measure. Two interesting findings emerged, the first that UK credit unions over-spend on dividend payments and the second that they under-spend on labour costs.

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An extensive experimental program has been carried out on a 135?mm tip diameter radial turbine using a variety of stator designs, in order to facilitate direct performance comparisons of varying stator vane solidity and the effect of varying the vaneless space. A baseline vaned stator was designed using commercial blade design software, having 15 vanes and a vane trailing edge to rotor leading edge radius ratio (Rte/rle) of 1.13. Two additional series of stator vanes were designed and manufactured; one series having varying vane numbers of 12, 18, 24, and 30, and a further series with Rte/rle ratios of 1.05, 1.175, 1.20, and 1.25. As part of the design process a series of CFD simulations were carried out in order to guide design iterations towards achieving a matched flow capacity for each stator. In this way the variations in the measured stage efficiency could be attributed to the stator passages only, thus allowing direct comparisons to be made. Interstage measurements were taken to capture the static pressure distribution at the rotor inlet and these measurements were then used to validate subsequent numerical models. The overall losses for different stators have been quantified and the variations in the measured and computed efficiency were used to recommend optimum values of vane solidity and Rte/rle.

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A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

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In DSP applications such as fixed transforms and filtering, the full flexibility of a general-purpose multiplier is not required and only a limited range of values is needed on one of the multiplier inputs. A new design technique has been developed for deriving multipliers that operate on a limited range of multiplicands. This can be used to produce FPGA implementations of DSP systems where area is dramatically improved. The paper describes the technique and its application to the design of a poly-phase filter on a Virtex FPGA. A 62% area reduction and 7% speed increase is gained when compared to an equivalent design using general purpose multipliers. It is also compared favourably to other known fixed coefficient approaches.