Application-Specific Instruction Set Processor for SoC implementation of Modern Signal Processing Algorithms

A novel application-specific instruction set processor (ASIP) for use in the construction of modern signal processing systems is presented. This is a flexible device that can be used in the construction of array processor systems for the real-time implementation of functions such as singular-value decomposition (SVD) and QR decomposition (QRD), as well as other important matrix computations. It uses a coordinate rotation digital computer (CORDIC) module to perform arithmetic operations and several approaches are adopted to achieve high performance including pipelining of the micro-rotations, the use of parallel instructions and a dual-bus architecture. In addition, a novel method for scale factor correction is presented which only needs to be applied once at the end of the computation. This also reduces computation time and enhances performance. Methods are described which allow this processor to be used in reduced dimension (i.e., folded) array processor structures that allow tradeoffs between hardware and performance. The net result is a flexible matrix computational processing element (PE) whose functionality can be changed under program control for use in a wider range of scenarios than previous work. Details are presented of the results of a design study, which considers the application of this decomposition PE architecture in a combined SVD/QRD system and demonstrates that a combination of high performance and efficient silicon implementation are achievable. © 2005 IEEE.

CORDIC based application-specific instruction set processor for QRD/SVD

An application specific programmable processor (ASIP) suitable for the real-time implementation of matrix computations such as Singular Value and QR Decomposition is presented. The processor incorporates facilities for the issue of parallel instructions and a dual-bus architecture that are designed to achieve high performance. Internally, it uses a CORDIC module to perform arithmetic operations, with pipelining of the internal recursive loop exploited to multiplex the two independent micro-rotations onto a single piece of hardware. The net result is a flexible processing element whose functionality can be changed under program control, which combines high performance with efficient silicon implementation. This is illustrated through the results of a detailed silicon design study and the applications of the techniques to a combined SVD/QRD system.

Generic Architecture and Semiconductor Intellectual Property Cores for Avanced Encryption Standard Cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.

Non-linear electronic transport in Pt nanowires deposited by focused ion beam

Electrical transport and structural properties of platinum nanowires, deposited using the focussed ion beam method have been investigated. Energy dispersive X-ray spectroscopy reveals metal-rich grains (atomic composition 31% Pt and 50% Ga) in a largely non-metallic matrix of C, O and Si. Resistivity measurements (15-300 K) reveal a negative temperature coefficient with the room-temperature resistivity 80-300 times higher than that of bulk Pt. Temperature dependent current-voltage characteristics exhibit non-linear behaviour in the entire range investigated. The conductance spectra indicate increasing non-linearity with decreasing temperature, reaching 4% at 15 K. The observed electrical behaviour is explained in terms of a model for inter-grain tunnelling in disordered media, a mechanism that is consistent with the strongly disordered nature of the nanowires observed in the structure and composition analysis.

Creation of damage-free ferroelectric nanocapacitors via focused ion beam milling

We present a novel method for creating damage-free ferroelectric nanostructures with a focused ion beam milling machine. Using a standard e-beam photoresist followed by a dilute acid wash, nanostructures ranging in size from 1 mu m down to 250 nm were created in a 90 nm thick lead zirconate titanate ( PZT) wafer. Transmission electron microscopy and piezoresponse force microscopy ( PFM) confirmed that the surfaces of the nanostructures remained damage free during fabrication, and showed no gallium implantation, and that there was no degradation of ferroelectric properties. In fact DC strain loops, obtained using PFM, demonstrated that the nanostructures have a higher piezoresponse than unmilled films. As the samples did not have any top hard mask, the method presented is unique as it allows for imaging of the top surface to understand edge effects in well-defined nanostructures. In addition, as no post-mill annealing was necessary, it facilitates investigation of nanoscale domain mechanisms without process-induced artefacts.