An efficient feature selection method for mobile devices with application to activity recognition

This paper presents a feature selection method for data classification, which combines a model-based variable selection technique and a fast two-stage subset selection algorithm. The relationship between a specified (and complete) set of candidate features and the class label is modelled using a non-linear full regression model which is linear-in-the-parameters. The performance of a sub-model measured by the sum of the squared-errors (SSE) is used to score the informativeness of the subset of features involved in the sub-model. The two-stage subset selection algorithm approaches a solution sub-model with the SSE being locally minimized. The features involved in the solution sub-model are selected as inputs to support vector machines (SVMs) for classification. The memory requirement of this algorithm is independent of the number of training patterns. This property makes this method suitable for applications executed in mobile devices where physical RAM memory is very limited. An application was developed for activity recognition, which implements the proposed feature selection algorithm and an SVM training procedure. Experiments are carried out with the application running on a PDA for human activity recognition using accelerometer data. A comparison with an information gain based feature selection method demonstrates the effectiveness and efficiency of the proposed algorithm.

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.