Architecture and Construction Management at Queens University Belfast:Regional Cultural Centre

The Regional Cultural Centre in Letterkenny is a new 2000sqm arts center containing theatre, galleries, workshops and ancillary offices. The site is set back from the street, on high ground with good views. The form and envelope of the building was derived from geometrically connecting the site with the town’s two other main public buildings, the Cathedral (1901) and new Civic Offices (2002, also designed by MacGabhann Architects). This geometrical connection or vectors informed the geometry and shape of the building. This urban matrix of geometrically connecting three corner stones of society, namely the ecclesiastical headquarters, the administrative head quarters and the art centre helps to improve the town planning and urban design of the disparate and chaotic development that Letterkenny has become.
The large cantilever, which houses a 300sqm gallery, is aligned towards the Civic Offices, marks the entrance, and signifies a change of direction of the pedestrian route past the building, like a modern day obelisk.
The circulation routes and stairs internally provide views towards the civic offices and cathedral, thus reinforcing the connection between the three buildings and helps visitors make some sense of Letterkenny as an urban center. The main stairs and vertical circulation are contained behind the large glazed foyer, which is framed to be viewed externally like a proscenium stage, with visitors to the building passively acting their routes through the building.

High performance VLSI architecture for division and square root

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

A versatile content addressable memory architecture

In this paper, a novel configurable content addressable memory (CCAM) cell is proposed, to increase the flexibility of embedded CAMs for SoC employment. It can be easily configured as a Binary CAM (BiCAM) or Ternary CAM (TCAM) without significant penalty of power consumption or searching speed. A 64x128 CCAM array has been built and verified through simulation. ©2007 IEEE.

A VLSI architecture for multiplication, division and square root

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

Bit-level systolic architecture for very high performance IIR filters

A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.

A bit-level systolic architecture for implementing a VQ tree search

A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system. © 1990 Kluwer Academic Publishers.

Reconfigurable full-search video motion estimation architecture

In this paper, a new reconfigurable multi-standard architecture is introduced for integer-pixel motion estimation and a standard-cell based chip design study is presented. This has been designed to cover most of the common block-based video compression standards, including MPEG-2, MPEG-4, H.263, H.264, AVS and WMV-9. The architecture exhibits simpler control, high throughput and relative low hardware cost and highly competitive when compared with excising designs for specific video standards. It can also, through the use of control signals, be dynamically reconfigured at run-time to accommodate different system constraint such as the trade-off in power dissipation and video-quality. The computational rates achieved make the circuit suitable for high end video processing applications. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards.

New FFT architecture and chip design for motion compensation based on phase correlation

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.