藏文字库标准符合性自动检测方案设计与实现

软件产品的标准符合性测试是衡量产品质量与性能的重要方法。本文根据藏文字符集标准与字型标准，按软件产品的可用性原则．分析与定义了藏文字库标准符合性检测的含义与内容。本文提出了实施藏文字库标准符合性测试的方案与算法，实现了藏文字库测试程序。测试结果表明本文的检测方案可行、完整，也为其他文字的字库标准符合性检测提供了很好的途径。

Phase variations and phase shift in a TE011 mode microwave cavity used for in a miniature Rb fountain frequency standard

It is the first time in China that the phase variations and phase shift of microwave cavity in a miniature Rb fountain frequency standard are studied, considering the effect of imperfect metallic walls. Wall losses in the microwave cavity lead to small traveling wave components that deliver power from the cavity feed to the walls of cavity. The small traveling wave components produce a microradian distribution of phase throughout the cavity ity, and therefore distributed cavity phase shifts need to be considered. The microwave cavity is a TE011 circular cylinder copper cavity, with round cut-hole of end plates (14mm in diameter) for access for the atomic flux and two small apertures in the center of the side wall for coupling in microwave power. After attenuation alpha is calculated, field variations in cavity are solved. The field variations of the cavity are given. At the same time, the influences of loaded quality factor QL and diameter/height (2a/d) of the microwave cavity on the phase variations and phase shift are considered. According to the phase variation and phase shift of microwave cavity we select the parameters of cavity, diameter 2a = 69.2mm, height d = 34.6mm, QL = 5000, which will result in an uncertainty delta(Delta f / f0 ) < 4.7 x 10(-17) and meets the requirement for the miniature Rb fountain frequency standard with accuracy 10(-15).

A Low-Voltage Silicon Light Emitting Device in Standard Salicide CMOS Technology

National Natural Science Foundation of China 60536030 60776024 60877035 90820002 National High-Technology Research and Development Program of China 2007AA04Z329 2007AA04Z254

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

Design of Low Power Multi-Standard Active-RC Filter for WLAN and DVB-H

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

A standard CMOS compatible monolithic photo-detector and trans-impedance amplifier

A 1GHz monolithic photo-detector (PD) and trans-impedance amplifier (TIA) is designed with the standard 0.35 mu m CMOS technique. The design of the photo-detector is analyzed and the CMOS trans-impedance amplifier is also analyzed in the paper. The integrating method is described too. The die photograph is also showed in the paper.

A silicon light emitting devices in standard CMOS technology

A silicon light emitting device is designed and simulated. It is fabricated in 0.6 mum standard CMOS technology. The device can give more than 1 muW optical power of visible light under reverse breakdown. The device can be turned on at a bias of 0.88 V and work in a large range of voltage: 1.0-6.0 V The external electrical-optical conversion efficiency is more than 10(-6). The optical spectrum of the device is between 540-650 nm, which have a clear peak near 580 nm. The emission mechanism can be explained by a hot carrier direct recombination model.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

A multi-standard active-RC filter with accurate tuning system

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architec-ture is presented. It exhibits 1EEE 802. 11a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 comer frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm~2 and 0.11 mm~2 (calibration circuit excluded), respectively.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

Low-temperature heat capacities and standard molar enthalpy of formation of aspirin

Molar heat capacities (C-p,C-m) of aspirin were precisely measured with a small sample precision automated adiabatic calorimeter over the temperature range from 78 to 383 K. No phase transition was observed in this temperature region. The polynomial function of Cp, vs. T was established in the light of the low-temperature heat capacity measurements and least square fitting method. The corresponding function is as follows: for 78 Kless than or equal toTless than or equal to383 K, C-p,C-m/J mol(-1) K-1=19.086X(4)+15.951X(3)-5.2548X(2)+90.192X+176.65, [X=(T-230.50/152.5)]. The thermodynamic functions on the base of the reference temperature of 298.15 K, {DeltaH(T)-DeltaH(298.15)} and {S-T-S-298.15}, were derived.