Whispering-gallery microcavity semiconductor lasers suitable for photonic integrated circuits and optical interconnects

The characteristics of whispering-gallery-like modes in the equilateral triangle and square microresonators are introduced, including directional emission triangle and square microlasers connected to an output waveguide. We propose a photonic interconnect scheme by connecting two directional emission microlasers with an optical waveguide on silicon integrated circuit chip. The measurement indicates that the triangle microlasers can work as a resonance enhanced photodetector for optical interconnect.

Superluminescent diode monolithically integrated with novel Y-branch by bundle integrated waveguide for fiber optic gyroscope - art. no. 68380D

We have developed a novel InP-based, ridge-waveguide photonic integrated circuit (PIC), which consists of a 1.1-um wavelength Y-branch optical waveguide with low loss and improved far field pattern and a 1.3-um wavelength strained InGaAsP-InP multiple quantum-well superluminescent diode, with bundle integrated guide (BIG) as the scheme for monolithic integration. The simulations of BIG and Y-branches show low losses and improved far-field patterns, based on the beam propagation method (BPM). The amplified spontaneous emission of the device is up to 10 mW at 120 mA with no threshold and saturation. Spectral characteristics of about 30 nm width and less than I dB modulation are achieved using the built-in anti-lasing ability of Y-branch. The beam divergence angles in horizontal and vertical directions are optimized to as small as 12 degrees x8 degrees, resulting in good fiber coupling. The compactness, simplicity in fabrication, good superluminescent performance, low transmission loss and estimated low coupling loss prove the BIG and Y-branch method to be a feasible way for integration and make the photonic integrated circuit of Y-branch and superluminescent diode an promising candidate for transmitter and transceiver used in fiber optic gyroscope.

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

A High Speed, 12-Channel Parallel, Monolithic Integrated CMOS OEIC Receiver

The design and fabrication of a high speed, 12-channel monolithic integrated CMOS optoelectronic integrated circuit(OEIC) receiver are reported.Each channel of the receiver consists of a photodetector,a transimpedance amplifier,and a post-amplifier.The double photodiode structure speeds up the receiver but hinders responsivity.The adoption of active inductors in the TIA circuit extends the-3dB bandwidth to a higher level.The receiver has been realized in a CSMC 0.6μm standard CMOS process.The measured results show that a single channel of the receiver is able to work at bit rates of 0.8～1.4Gb/s. Altogether, the 12-channel OEIC receiver chip can be operated at 15Gb/s.

Small signal equivalent circuit model of vertical cavity surface emitting lasers

Small signal equivalent circuit model of vertical cavity surface emitting lasers (VCSEL's) is given in this paper. The modulation properties of VCSEL are simulated using this model in Pspice program. The simulation results are good agree with experiment data. Experiment is performed to testify the circuit model.

Integrated multimode interference couplers in silicon-on insulator

Silicon-on insulator (SOI) is an attractive platform for the fabrication of optoelectronic integrated circuit. Thin cladding layers (< 1.0m) can be used in SOI waveguide due to the large index step between Si and SiO2, making them compatible with the VLSI technology. Here we demonstrate the fabrication of 1 x 4 and 2 x 2 multimode interference (MMI) coupler based on SOI technology. Performances of the devices are analyzed. The minimum excess loss of the devices is about 1.8dB. The devices show uniform power distribution.

Materials selection in mechanical design for microsensors and microactuators

Microsensors and microactuators are vital organs of microelectromechanical systems (MEMS), forming the interfaces between controller and environment. They are usually used for devices ranging in size at sub-millimeter or micrometer level, transforming energy between two or more domains. Presently, most of the materials used in MEMS devices belong to the silicon material system, which is the basis of the integrated circuit industry. However, new techniques are being explored and developed, and the opportunities for MEMS materials selection are getting broader. The present paper tries to apply 'performance index' to select the material best suited to a given application, in the early stage of MEMS design. The selection is based on matching performance characteristics to the requirements. A series of performance indices are given to allow a wide range comparison of materials for several typical sensing and actuating structures, and a rapid identification of candidates for a given task. (C) 2002 Elsevier Science Ltd. All rights reserved.

一种改进型金属-半导体-金属光电探测器数学模型

以E. Sano的金属-半导体-金属光电探测器(MSM-PD)模型为基础,提出了一种改进型的模型。该模型以多个电流源和电容并联的形式构造,以吸收区过剩电子和空穴总数为研究对象,求解速率方程。另外计算了电容,给出了暗电流与端电压的非线性计算式,改进了传统模型中暗电流的线性计算方法。通过线性叠加给出了该模型光电流的数学解析解。通过在Matlab中的模拟计算,表明该模型具有计算量小、准确度高的特点,它不仅能反映一定偏压和光照下光电流的变化,而且能展示光电子在器件中的转化过程。这种模型也能较好地应用于微弱信号的检

Development of solar-blind AlGaN 128x128 ultraviolet focal plane arrays

This paper reports the development of solar-blind aluminum gallium nitride (AlGaN) 128x128 UV Focal Plane Arrays (FPAs). The back-illuminated hybrid FPA architecture consists of an 128x128 back-illuminated AlGaN PIN detector array that is bump-mounted to a matching 128x128 silicon CMOS readout integrated circuit (ROIC) chip. The 128x128 p-i-n photodiode arrays with cuton and cutoff wavelengths of 233 and 258 nm, with a sharp reduction in response to UVB (280-320 nm) light. Several examples of solar-blind images are provided. This solar-blind band FPA has much better application prospect.

Single-electron tunneling depressing synapse for cellular neural networks

In this paper, a cellular neural network with depressing synapses for contrast-invariant pattern classification and synchrony detection is presented, starting from the impulse model of the single-electron tunneling junction. The results of the impulse model and the network are simulated using simulation program with integrated circuit emphasis (SPICE). It is demonstrated that depressing synapses should be an important candidate of robust systems since they exhibit a rapid depression of excitatory postsynaptic potentials for successive presynaptic spikes.