Realization of negative differential resistance and switching devices based on copper phthalocyanine by the control of evaporation rate

We have observed, respectively, a negative differential resistance (NDR) and switching conduction in current-voltage (I-V) characteristics of organic diodes based on copper phthalocyanine (CuPc) film sandwiched between indium-tin-oxide (ITO) and aluminum (Al) by controlling the evaporation rate. The NDR effect is repeatable which can be well, controlled by sweep rate and start voltage, and the switching exhibits write-once-read-many-times (WORM) memory characteristics. The traps in the organic layer and interfacial dipole have been used to explain the NDR effect and switching conduction. This opens up potential applications for CuPc organic semiconductor in low power memory and logic circuits.

Electrical properties in vanadyl-phthalocyanine-based metal-insulator-semiconductor devices

We investigated electrical properties of vanadyl phthalocyanine (VOPc) metal-insulator-semiconductor (MIS) devices by the measurement of capacitance and conductance, which were fabricated on ordered para-sexiphenyl (p-6P) layer by weak epitaxy growth method. The VOPc/p-6P MIS diodes showed a negligible hysteresis effect at a gate voltage of +/- 20 V and small hysteresis effect at a gate voltage of +/- 40 V due to the low interface trap state density of about 1x10(10) eV(-1) cm(-2). Furthermore, a high transition frequency of about 10 kHz was also observed under their accumulation mode. The results indicated that VOPc was a promising material and was suitable to be applied in active matrix liquid crystal displays and organic logic circuits.

Negative differential resistance effect in organic devices based on an anthracene derivative

The authors observed a negative differential resistance (NDR) in organic devices consisting of 9,10-bis-(9,9-diphenyl-9H-fluoren-2-yl)-anthracene (DPFA) sandwiched between Ag and indium tin oxide electrodes. The large NDR shown in current-voltage characteristics is reproducible, resulting in that the organic devices can be electrically switched between a high conductance state (on state) and a low conductance state (off state). It can be found that the currents at both on to off states are space-charge limited and attributed to the electron traps at the Ag/DPFA interface. The large and reproducible NDR makes the devices of tremendous potential in low power memory and logic circuits.

Negative differential resistance and multilevel memory effects in organic devices

Negative differential resistance ( NDR) and multilevel memory effects were obtained in organic devices consisting of an anthracene derivative, 9,10-bis-{ 9,9-di-[ 4-(phenyl-p-tolyl-amino)-phenyl]-9H-fluoren-2-yl}-anthracene ( DAFA), sandwiched between Ag and ITO electrodes. The application of a negative bias voltage leads to negative differential resistance in current-voltage characteristics and different negative voltages produce different conductance currents, resulting in the multilevel memory capability of the devices. The NDR property has been attributed to charge trapping at the DAFA/Ag interface. This opens up a wide range of application possibilities of such organic-based NDR devices in memory and logic circuits.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Monostable-Bistable Transition Logic Element (MOBILE) Model for Single-Electron Transistors

The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Potassium-Lead-Switched G-Quadruplexes: A New Class of DNA Logic Gates

A cation-driven allosteric G-quadruplex DNAzyme (PW17) was utilized to devise a conceptually new class of DNA logic gate based on cation-tuned ligand binding and release. K+ favors the binding of hemin to parallel-stranded PW17, thereby promoting the DNAzyme activity, whereas Pb2+ induces PW17 to undergo a parallel-to-antiparallel conformation transition and thus drives hemin to release from the G-quadruplex, deactivating the DNAzyme. Such a K+-Pb2+ switched G-quadruplex, in fact, functions as a two-input INHIBIT logic gate. With the introduction of another input EDTA, this G-quadruplex can be further utilized to construct a reversibly operated IMPLICATION gate.

Application of sample-and-hold circuits in the laser frequency-shifting

A new method of frequency-shifting for a diode laser is realized. Using a sample-and-hold circuit, the error signal can be held by the circuit during frequency shifting. It can avoid the restraint of locking or even lock-losing caused by the servo circuit when we input a step-up voltage into piezoelectric transition (PZT) to achieve laser frequency-shifting.

Parallel optical negabinary arithmetic based on logic operations

On the basis of signed-digit negabinary representation, parallel two-step addition and one-step subtraction can be performed for arbitrary-length negabinary operands.; The arithmetic is realized by signed logic operations and optically implemented by spatial encoding and decoding techniques. The proposed algorithm and optical system are simple, reliable, and practicable, and they have the property of parallel processing of two-dimensional data. This leads to an efficient design for the optical arithmetic and logic unit. (C) 1997 Optical Society of America.

Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio. (C) 1999 Optical Society of America.

Logic-operated mathematical morphology and its optical implementation

A more powerful tool for binary image processing, i.e., logic-operated mathematical morphology (LOMM), is proposed. With LOMM the image and the structuring element (SE) are treated as binary logical variables, and the MULTIPLY between the image and the SE in correlation is replaced with 16 logical operations. A total of 12 LOMM operations are obtained. The optical implementation of LOMM is described. The application of LOMM and its experimental results are also presented. (C) 1999 Optical Society of America.