对DES的Rectangle攻击和Boomerang攻击

作为加密标准，DES（data encryption standard）算法虽然已被AES（advanced encryption standard）算法所取代，但其仍有着不可忽视的重要作用．在一些领域，尤其是金融领域，DES和Triple DES仍被广泛使用着．而近年来又提出了一些新的密码分析方法，其中，Rectangle攻击和Boomerang攻击已被证明是非常强大而有效的．因此，有必要重新评估DES算法抵抗这些新分析方法的能力．研究了DES算法针对Rectangle攻击和Boomerang攻击的安全性．利用DES各轮最优差分路径及其概率，分别得到了对12轮DES的Rectangle攻击和对11轮DES的Boomerang攻击．攻击结果分别为：利用Rectangle攻击可以攻击到12轮DES，数据复杂度为2~(62)。个选择明文，时间复杂度为2~(42)次12轮加密；利用Boomerang攻击可以攻击到11轮DES，数据复杂度为2~(58)个适应性选择明密文，时间复杂度为2~(38)次11轮加密．由于使用的都是DES各轮的最优差分路径，所以可以相信，该结果是Rectangle攻击和Boomerang攻击对DES所能达到的最好结果．

韩国加密标准的安全性分析

SEED是韩国的数据加密标准，设计者称用线性密码分析攻击SEED的复杂度为2^335.4，而用本文构造的15轮线性逼近攻击SEED的复杂度为2^328．为了说明SEED抵抗差分密码分析的能力，设计者首先对SEED的变体SEED‘做差分密码分析，指出9轮SEED*对差分密码分析是安全的；利用SEED^*的扩散置换和盒子的特性，本文构造SEED^*的9轮截断差分，因此10轮SEED^*对截断差分密码分析是不免疫的．本文的结果虽然对SEED的实际应用构成不了威胁，但是显示了SEED的安全性并没有设计者所称的那样安全．

Phase variations and phase shift in a TE011 mode microwave cavity used for in a miniature Rb fountain frequency standard

It is the first time in China that the phase variations and phase shift of microwave cavity in a miniature Rb fountain frequency standard are studied, considering the effect of imperfect metallic walls. Wall losses in the microwave cavity lead to small traveling wave components that deliver power from the cavity feed to the walls of cavity. The small traveling wave components produce a microradian distribution of phase throughout the cavity ity, and therefore distributed cavity phase shifts need to be considered. The microwave cavity is a TE011 circular cylinder copper cavity, with round cut-hole of end plates (14mm in diameter) for access for the atomic flux and two small apertures in the center of the side wall for coupling in microwave power. After attenuation alpha is calculated, field variations in cavity are solved. The field variations of the cavity are given. At the same time, the influences of loaded quality factor QL and diameter/height (2a/d) of the microwave cavity on the phase variations and phase shift are considered. According to the phase variation and phase shift of microwave cavity we select the parameters of cavity, diameter 2a = 69.2mm, height d = 34.6mm, QL = 5000, which will result in an uncertainty delta(Delta f / f0 ) < 4.7 x 10(-17) and meets the requirement for the miniature Rb fountain frequency standard with accuracy 10(-15).

A Low-Voltage Silicon Light Emitting Device in Standard Salicide CMOS Technology

National Natural Science Foundation of China 60536030 60776024 60877035 90820002 National High-Technology Research and Development Program of China 2007AA04Z329 2007AA04Z254

Status and trends of short pulse generation using mode-locked lasers based on advanced quantum-dot active media

In this review, the potential of mode-locked lasers based on advanced quantum-dot ( QD) active media to generate short optical pulses is analysed. A comprehensive review of experimental and theoretical work on related aspects is provided, including monolithic-cavity mode-locked QD lasers and external-cavity mode-locked QD lasers, as well as mode-locked solid-state and fibre lasers based on QD semiconductor saturable absorber mirrors. Performance comparisons are made for state-of-the-art experiments. Various methods for improving important characteristics of mode-locked pulses such as pulse duration, repetition rate, pulse power, and timing jitter through optimization of device design parameters or mode-locking methods are addressed. In addition, gain switching and self-pulsation of QD lasers are also briefly reviewed, concluding with the summary and prospects.

Monolithic Integration of Light Emitting Diodes, Photodetector and Receiver Circuit in Standard CMOS Technology

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

Design of Low Power Multi-Standard Active-RC Filter for WLAN and DVB-H

In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

A standard CMOS compatible monolithic photo-detector and trans-impedance amplifier

A 1GHz monolithic photo-detector (PD) and trans-impedance amplifier (TIA) is designed with the standard 0.35 mu m CMOS technique. The design of the photo-detector is analyzed and the CMOS trans-impedance amplifier is also analyzed in the paper. The integrating method is described too. The die photograph is also showed in the paper.

A silicon light emitting devices in standard CMOS technology

A silicon light emitting device is designed and simulated. It is fabricated in 0.6 mum standard CMOS technology. The device can give more than 1 muW optical power of visible light under reverse breakdown. The device can be turned on at a bias of 0.88 V and work in a large range of voltage: 1.0-6.0 V The external electrical-optical conversion efficiency is more than 10(-6). The optical spectrum of the device is between 540-650 nm, which have a clear peak near 580 nm. The emission mechanism can be explained by a hot carrier direct recombination model.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).