Quantum mechanical effects in nanometer field effect transistors

The atomistic pseudopotential quantum mechanical calculations for million atom nanosized metal-oxide-semiconductor field-effect transistors (MOSFETs) are presented. When compared with semiclassical Thomas-Fermi simulation results, there are significant differences in I-V curve, electron threshold voltage, and gate capacitance. In many aspects, the quantum mechanical effects exacerbate the problems encountered during device minimization, and it also presents different mechanisms in controlling the behaviors of a nanometer device than the classical one. (c) 2007 American Institute of Physics.

Novel hybrid voltage controlled ring oscillators using single electron and MOS transistors

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.

Comparison of two kinds of active layers for high-power narrow-stripe distributed feedback laser diodes

Usually GaAs/AlGaAs is utilized as an active layer material in laser diodes operating in the spectral range of 800 850 nm. In this work, in addition to a traditional unstrained GaAs/AlGaAs distributed feedback (DFB) laser diode, a compressively strained InGaAlAs/AlGaAs DFB laser diode is numerically investigated in characteristic. The simulation results show that the compressively strained DFB laser diode has a lower transparency carrier density, higher gain, lower Auger recombination rate, and higher stimulated recombination rate, which lead to better a device performance, than the traditional unstrained GaAs/AlGaAs DFB laser diode.

Geometry parameter optimization of large cross-sectional S-shaped bent rib waveguides for silicon based optical switches

地址: Chinese Acad Sci, Inst Semicond, State Key Lab Integrated Optoelect, Beijing 100083, Peoples R China

Emitter of hetero-junction solar cells created using pulsed rapid thermal annealing

In this paper, we use a pulsed rapid thermal processing (RTP) approach to create an emitter layer of hetero-junction solar cell. The process parameters and crystallization behaviour are studied. The structural, optical and electric properties of the crystallized films are also investigated. Both the depth of PN junction and the conductivity of the emitter layer increase with the number of RTP pulses increasing. Simulation results show that efficiencies of such solar cells can exceed 15% with a lower interface recombination rate, but the highest efficiency is 11.65% in our experiments.

Light-propagation characteristics of photonic crystal waveguide based on SOI materials at different polarized states

Straight single-line defect optical waveguides in photonic crystal slabs are designed by the plane wave expansion method and fabricated into silicon-on-insulator (SOI) wafer by 248-nm deep UV lithography. We present an efficient way to measure the light transmission spectrum of the photonic crystal waveguide (PhC WG) at given polarization states. By employing the Mueller/Stokes method, we measure and analyse the light propagation properties of the PhC WG at different polarized states. It is shown that experimental results are in agreement with the simulation results of the three-dimensional finite-difference-time-domain method.

Stability improvement of selective oxidation during the fabrication of InGaAs/GaAs vertical cavity surface emitting laser

The effects of the carrier gas flow and water temperature on the oxidation rate for different reaction temperatures were investigated. The optimum conditions for stable oxidation were obtained. Two mechanisms of the oxidation process are revealed. One is the flow-controlling process, which is unstable. The other is the temperature-controlling process, which is stable. The stable region decreases for higher reaction temperatures. The simulation results for the stable oxidation region are also given. With optimum oxidation conditions, the stability and precision of the oxidation can be dramatically improved.

Design considerations for a silicon-based p-i-n phase modulator in a double ridge waveguide with side isolating grooves

We present detail design considerations and simulation results of a forward biased carrier injection p-i-n modulator integrated on SOI rib waveguides. To minimize the free carrier absorption loss while keeping the comparatively small lateral dimensions of the modulator as required for high speed operation, we proposed two structural improvements, namely the double ridge (terrace ridge) structure and the isolating grooves at both sides of the double ridge. With improved carrier injection and optical confinement structure, the simulated modulator response time is in sub-ns range and absorption loss is minimized.

High speed silicon optical switches based on carrier depletion - art. no. 67812D

The novel design of a silicon optical switch on the mechanism of a reverse p-n junction is proposed. The figuration of contact regions at slab waveguides and the ion implantation technology for creation of junctions are employed in the new design. The two-layer rib structure is helpful for reduction of optical absorption losses induced by metal and heavily-doped contact. And more, simulation results show that the index modulation efficiency of Mach-Zehnder interferometer enhances as the concentrations of dopants in junctions increase, while the trade-off of absorption loss is less than 3 dB/mu m. The phase shift reaches about 5 x 10(-4) pi/mu m at a reverse bias of 10V with the response time of about 0.2ns. The preliminary experimental results are presented. The frequency bandwidth of modulation operation can arrive in the range of GHz. However, heavily-doped contacts have an important effect on pulse response of these switches. While the contact region is not heavily-doped, that means metal electrodes have schottky contacts with p-n junctions, the operation bandwidth of the switch is limited to about 1GHz. For faster response, the heavily-doped contacts must be considered in the design.

Monostable-Bistable Transition Logic Element (MOBILE) Model for Single-Electron Transistors

The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

AN EFFICIENT ITERATIVE DFT-BASED CHANNEL ESTIMATION FOR MIMO-OFDM SYSTEMS ON MULTIPATH CHANNELS

In this paper, an efficient iterative discrete Fourier transform (DFT) -based channel estimator with good performance for multiple-input and multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems such as IEEE 802.11n which retain some sub-carriers as null sub-carriers (or virtual carriers) is proposed. In order to eliminate the mean-square error (MSE) floor effect existed in conventional DFT-based channel estimators, we proposed a low-complexity method to detect the significant channel impulse response (CIR) taps, which neither need any statistical channel information nor a predetermined threshold value. Analysis and simulation results show that the proposed method has much better performance than conventional DFT-based channel estimators and without MSE floor effect.

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.