Purification of single-walled carbon nanotubes synthesized by the catalytic decomposition of hydrocarbons

A procedure for purifying single-walled carbon nanotubes (SWNTs) synthesized by the catalytic decomposition of hydrocarbons has been developed. Based on the results from SEM observations, EDS analysis and Raman measurements, it was found that amorphous carbon, catalyst particles, vapor-grown carbon nanofibers and multi-walled carbon nanotubes were removed from the ropes of SWNTs without damaging the SWNT bundles, and a 40% yield of the SWNTs with a purity of about 95% was achieved after purification. (C) 2000 Elsevier Science Ltd. All rights reserved.

The new exploration for proton-implanted silicon: the conversion of a surface-region-purification-induced p-n junction into a p-i-n electrical structure approaching silicon on insulator

A surface-region-purification-induced p-n junction, a puzzle discovered at Brookhaven National Laboratory, in a silicon-on-defect-layer (SODL) material has been explored by carrying out various annealing conditions and subsequent measurements on electrical properties. The origin of the pn junction has been experimentally investigated. Furthermore, the p-n junction has been transformed into a p-i-n electrical structure by adding a high temperature annealing process to the previously used SODL procedure, making the SODL material approach silicon on insulator (SOI). The control of the initial oxygen amount in the silicon material is suggested to be critical for the experimental results.

Performing Fast Addition and Multiplication by Transferring Single Electrons

This paper proposes novel fast addition and multiplication circuits that are based on non-binary redundant number systems and single electron (SE) devices. The circuits consist of MOSFET-based single-electron (SE) turnstiles. We use the number of electrons to represent discrete multiple-valued logic states and we finish arithmetic operations by controlling the number of electrons transferred. We construct a compact PD2,3 adder and a 12x12bit multiplier using the PD2,3 adder. The speed of the adder can be as high as 600MHz with 400nW power dissipation. The speed of the adder is regardless of its operand length. The proposed circuits have much smaller transistors than conventional circuits.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer

This paper proposes a smart frequency presetting technique for fast lock-in LC-PLL frequency synthesizer. The technique accurately presets the frequency of VCO with small initial frequency error and greatly reduces the lock-in time. It can automatically compensate preset frequency variation with process and temperature. A 2.4GHz synthesizer with 1MHz reference input was implemented in 0.35 mu m CMOS process. The chip core area is 0.4mm(2). Output frequency of VCO ranges from 2390 to 2600MHz. The measured results show that the typical lock-in time is 3 mu s. The phase noise is -112dBc/Hz at 600KHz offset from center frequency. The test chip consumes current of 22mA that includes the consumption of the I/O buffers.

Fast Discrimination of Commerical Corn Varieties Based on Near Infrared Spectra

The existing methods for the discrimination of varieties of commodity corn seed are unable to process batch data and speed up identification, and very time consuming and costly. The present paper developed a new approach to the fast discrimination of varieties of commodity corn by means of near infrared spectral data. Firstly, the experiment obtained spectral data of 37 varieties of commodity corn seed with the Fourier transform near infrared spectrometer in the wavenurnber range from 4 000 to 12 000 cm (1). Secondly, the original data were pretreated using statistics method of normalization in order to eliminate noise and improve the efficiency of models. Thirdly, a new way based on sample standard deviation was used to select the characteristic spectral regions, and it can search very different wavenumbers among all wavenumbers and reduce the amount of data in part. Fourthly, principal component analysis (PCA) was used to compress spectral data into several variables, and the cumulate reliabilities of the first ten components were more than 99.98%. Finally, according to the first ten components, recognition models were established based on BPR. For every 25 samples in each variety, 15 samples were randomly selected as the training set. The remaining 10 samples of the same variety were used as the first testing set, and all the 900 samples of the other varieties were used as the second testing set. Calculation results showed that the average correctness recognition rate of the 37 varieties of corn seed was 94.3%. Testing results indicate that the discrimination method had higher precision than the discrimination of various kinds of commodity corn seed. In short, it is feasible to discriminate various varieties of commodity corn seed based on near infrared spectroscopy and BPR.