A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-04-13T02:59:28Z No. of bitstreams: 1 A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation.pdf: 9576536 bytes, checksum: 5b0e756cbabd4968f16dd05f6f076d30 (MD5)

Made available in DSpace on 2010-04-13T02:59:28Z (GMT). No. of bitstreams: 1 A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation.pdf: 9576536 bytes, checksum: 5b0e756cbabd4968f16dd05f6f076d30 (MD5) Previous issue date: 2009

IEEE Beijing Sect.; Fudan Univ.; IEEE China Council.; Natl Univ Def Tech.; IEEE CAS, IEEE SSCS.; Chinese Inst Elect.

其它

IEEE Beijing Sect.; Fudan Univ.; IEEE China Council.; Natl Univ Def Tech.; IEEE CAS, IEEE SSCS.; Chinese Inst Elect.