Compact polarization-insensitive arrayed waveguide grating based on SOI material

A compact polarization-insensitive 8x8 arrayed waveguide grating with 100GHz channel spacing at 1.55 mu m is presented on the material of silicon on insulator (SOI). Increasing the epitaxial layer thickness can reduce the birefringence of the waveguide, but the wvaeguide's bend radius also increases at the same time. We choose the SOI wafer with 3.0 mu m epitaxial layer to reduce the device's size and designed the appropriate structure of rib wave-guides to eliminate the polarization dependant wavelength shift. Compared to the other methods of eliminating the polarization dependant wavelength shift, the method is convenient and easy to control the polarization without additional etching process. The index differences between TE0 and TM0 of straight and bend waveguides are 1.4x10(-5) and 3.9x10(-5), respectively. The results showed that the polarization dependant wavelength shift is 0.1nm, and the device size is 1.5x1.0 cm(2).

Effect of the implantation of fluorine on the mobility of channel electron for partially depleted SOI nMOSFET

The mobility of channel electron, for partially depleted Sol nMOSFET in this paper, decreases with the increase of implanted fluorine dose in buried oxide layer. But, the experimental results also show that it is larger for the transistor corresponding to the lowest implantation dose than no implanted fluorine in buried layer. It is explained in tern-is of a "lubricant" model. Mien fluorine atoms are implanted in the top silicon layer, the mobility is the largest. In addition, a positive shift of threshold voltage has also been observed for the transistors fabricated on the Sol wafers processed by the implantation of fluorine. The causes of all the above results are discussed.

A simulation model of body contact structure in PD SOI analogue circuit

As a solution of accurate simulation of the body effect in PD SOI analogue circuit, a simulation model of distributed body contact resistance and parasitical capacitance is presented. Based on this model, we have designed and simulated a sense amplifier that applied to V a 0.8um PD SOI 64K SRAM.

Structural optimizations of SOI-based single-mode rib waveguide bends

Effects of structure parameters on bend loss of rib silicon-on-insulator (Sol) bend waveguides have been analyzed by means of effective index method (EIM) and 2D bend loss formula. The simulation results indicate that the bend loss decreases with the increase of bend radius and waveguide width, as well as with the decrease of the step factor of the rib waveguide. Moreover, the optional structure parameters have been found when bend waveguides are single-mode.

A low power consumption thermo-optic variable optical attenuator based on SOI material

A SOI thenno-optic variable optical attenuator with U-grooves based on a multimode interference coupler principle is fabricated. The dynamic attenuation range is 0 to 29 dB; at the wavelength range between 1510 nm and 1610nm, and the maximum power consumption is only l30mW. Compared to the variable optical attenuator without U-groove, the maximum power consumption decreases more than 230mW

The effect of Fabry-Perot interference on the packaging of SOI-based optoelectronic devices

During the packaging of optoelectrome device, a problem always met is the instability of output power. The main effect causing this problem, Fabry-Perot interference, is discussed in this paper. Both theoretical analysis and experimental test are carried out and in good agreement. As an example of avoiding the disadvantage of Fabry-Perot interference, the packaging process of Silicon-on-Insulator (SOI) based Variable Optical Attenuator(VOA) is shown at last.

High-Order Microring Filters on SOI Wafer

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High-Saturation-Power and High-Speed Ge-on-SOI p-i-n Photodetectors

Ge-on-silicon-on-insulator p-i-n photodetectors were fabricated using an ultralow-temperature Ge buffer by ultrahigh-vacuum chemical vapor deposition. For a detector of 70-mu m diameter, the 1-dB small-signal compression power was about 110.5 mW. The 3-dB bandwidth at 3-V reverse bias was 13.4 GHz.

THE DEPENDENCE OF THE INVERSION LAYER THICKNESS ON THE FILM THICKNESS IN THIN-FILM SOI STRUCTURES

The dependence of the inversion-layer thickness on the film thickness in thin-film SOI structure is analyzed theoretically by using computer simulation. A new concept and parameter, the critical thickness of thin film all-bulk inversion, is introduced for the design of thin-film MOS/SOI devices. It is necessary to select the film thickness T(s1) close to the all-bulk strong inversion critical thickness in order to get high-speed and high-power operation of ultra-thin film MOS/SOI devices.

4×4热光SOI波导开关阵列

设计并制作了阻塞型和完全无阻塞型4×4热光SOI(silicon-on-insulator)波导开关阵列.开关单元采用了多模干涉耦合器(MMI)-MZI(Mach-Zehnder intederometer)结构的2×2光开关.阻塞型光开关附加损耗为4.8～5.4 dB,串扰为-21.8 dB～-14.5 dB.完全无阻塞型光开关阵列附加损耗为6.6～9.6 dB,串扰为-25.8～-16.8 dB.两者的消光比都在17～25 dB内变化,开关单元功耗小于230 mW.器件的开关时间小于3μs.功耗和开关速度都明显优于SiO_2基和聚合物基的开关阵列.

高阶布拉格光栅在SOI脊形波导上的光刻制作

在SOI脊形波导上通过光刻的方法制作了高阶布拉格光栅.采用顶层Si厚为2μm的SOI基片,通过半导体芯片制备中的光刻工艺,在脊高为935 nm,波导宽度为2μm的脊形波导上,分别制作了刻蚀深度为565 nm和935 nm的起伏型高阶布拉格光栅,测试表明,在1540～1640 nm波长范围内,得到了大于10 dB的消光比,实现了高阶布拉格光栅在SOI脊形波导上的滤波效果.理论和实验都证明了光栅刻蚀深度的增大将有利于增加高阶布拉格光栅的耦合系数,以及光栅周期数的增加会引起更大的光栅损耗.

基于SOI硅片的硅微电极制作与评估

采用微机电系统(MEMS)工艺方法制作了基于SOI衬底的七通道硅微电极,用于视神经视觉修复.通过噪声分析确定了硅微电极的金属暴露位点的几何尺寸.优化设计了硅微电极的几何结构,以便于减小植入损伤.阻抗测试结果表明,当测试电压为50mVpp时,1kHz频率下,微电极的单通道阻抗为2.3MQ,适用于神经电信号记录.在体实验结果表明,动物初级视皮层记录到的神经电信号幅度为8μV.

8×8重排无阻塞型SOI热光波导开关阵列

设计并制作了一种重排无阻塞型的8×8 SOI热光波导开关阵列。开关单元采用了MM I-MZI结构的2×2光开关。整个器件的开关时间约为2μs。器件中开关单元功耗小于240mW。消光比在17~22dB范围内变化。功耗和开关速度都明显优于SiO2基和聚合物基的开关阵列。

Triplexers Based on SOI Flattop AWGs

Triplexers are designed based on SOl flattop arrayed waveguide gratings （AWGs）. Three wavelengths （1310, 1490,and 1550nm） operate at three diffraction orders of AWGs. Simulation shows that the 3dB bandwidth,crosstalk, and loss are 6nm,less than -40dB, and 5dB, respectively. The output optical fields of the device fabricated in our laboratory are clear and show a good triplexing function.