93 resultados para Fast test


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The exact calculation of mode quality factor Q is a key problem in the design of high-Q photonic crystal nanocavity. On the basis of further investigation on conventional Pade approximation, FDM and DFT, Pade approximation with Baker's algorithm is enhanced through introducing multiple frequency search and parabola interpolation. Though Pade approximation is a nonlinear signal processing method and only short time sequence is needed, we find the different length of sequence requirements for 2D and 3D FDTD, which is very important to obtain convergent and accurate results. By using the modified Pade approximation method and 3D FDTD, the 2D slab photonic crystal nanocavity is analyzed and high-Q multimode can be solved quickly instead of large range high-resolution scanning. Monitor position has also been investigated. These results are very helpful to the design of photonic crystal nanocavity devices. (C) 2008 Elsevier B.V. All rights reserved.

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This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.

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A thermo-optic variable optical attenuator module composed of a silicon-on-insulator attenuator chip and driving circuit was designed and fabricated. The module exhibited a maximum attenuation of 21.8 dB and a response time of 10 mu s. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

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A rearrangeable nonblocking 4 x 4 thermooptic silicon-on-insulator waveguide switch matrix at 1.55-mu m integrated spot size converters is designed and fabricated for the first time. The insertion losses and polarization-dependent losses of the four channels are less than 10 and 0.8 dB, respectively. The extinction ratios are larger than 20 dB. The response times are 4.6 mu s for rising edge and 1.9 mu s for failing edge.

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A silicon-on-insulator-based thermo-optic waveguide switch integrated with spot size converters is designed and fabricated by inductively coupled plasma reactive ion etching. The device shows good characteristics, including low, insertion loss of 8 +/- 1 dB for wavelength 1530-1580 nm and fast response times of 4.6 As for rising edge and 1.9 mu s for failing edge. The extinction ratios of the two channels are 19.1 and 18 dB, respectively.

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Three known standards, including at least one transmission standard, are normally required for the full two-port calibration of test fixtures. Based on the triple-through method, a new general-purpose calibration procedure using only one known reflection standard is proposed in this paper. The experimental results show that our method call provide a simple and accurate approach to fall two-port calibration of the asymmetric test fixtures. (c) 2005 Wiley Periodicals, Inc.

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A low power consumption 2 x 2 thermo-optic switch with fast response was fabricated on silicon-on-insulator by anisotropy chemical etching. Blocking trenches were etched on both sides of the phase-shifting arms to shorten device length and reduce power consumption. Thin top cladding layer was grown to reduce power consumption and switching time. The device showed good characteristics, including a low switching power of 145 mW and a fast switching speed of 8 +/- 1 mus, respectively. Two-dimensional finite element method was applied to simulate temperature field in the phase-shifting arm instead of conventional one-dimensional method. According to the simulated result, a new two-dimensional index distribution of phase-shifting arm was determined. Consequently finite-difference beam propagation method was employed to simulate the light propagation in the switch, and calculate the power consumption as well as the switching speed. The experimental results were in good agreement with the theoretical estimations. (C) 2004 Elsevier B.V. All rights reserved.

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Based on thermo-optical effect of silicon, a 2 x 2 switch is fabricated in silicon-on-insulator by chemical etching. The switch presents an extinction ratio of 26 dB and a power consumption of 169 mW. The response time F similar to 10.5 mus.

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We present a linear-cavity stretched-pulse fibre laser with mode locking by a nonlinear polarization rotation and by semiconductor saturable-absorber mirrors. A Q-switched mode-locking cw train and a mode-locking pulse train are obtained in the experiment. We investigate the effects of the equivalent fast saturable absorber and the slow saturable absorbers in experiment. It is found that neither the nonlinear polarization evolution effect nor a semiconductor saturable absorber mirror is enough to produce the stable cw mode-locking pulses in this experiment. A nonlinear polarization evolution effect controls the cavity loss to literally carve the pulses; semiconductor saturable absorber mirrors provide the self-restarting and maintain the stability of the mode-locking operation.

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This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

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The problem of frequency limitation arising from the calibration of asymmetric and symmetric test fixtures has been investigated. For asymmetric test fixtures, a new algorithm based on the thru-short-match (TSM) method is outlined. It is found that the conventional TSM method does not have any inherent frequency limitation, but using the same procedure with an unknown match may lead to the said problem. This limitation can be avoided by using a different algorithm. The various calibration methods for symmetric test fixtures using known standards are also discussed and the origin of the frequency limitation is identified. Several ways in avoiding the problem are proposed. There is good agreement between the theories and experimental data.

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The open-short-load (OSL) method is very simple and widely used for one-port test fixture calibration. In this paper, this method is extended, for the first time, to the two-port calibration of test fixtures with different test ports. The problem of phase uncertainty arising in this application has been solved. The comparison between our results and those obtained with the SOLT method shows that the method established is accurate for practical applications. (C) 2002 Wiley Periodicals, Inc.

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Based on the conventional through-short-match (TSM) method, an improved TSM method has been proposed in this Letter. This method gives an analytical solution and has almost all the advantages of conventional TSM methods. For example, it has no phase uncertainty and no bandwidth limitation. The experimental results show that the accuracy can be significantly improved with this method. The proposed theory can be applied to the through-open-match (TOM) method. (C) 2002 Wiley Periodicals. Inc.

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The problem of phase uncertainty arising in calibration of the test fixtures is investigated in this paper, It is shown that the problem exists no matter what kinds of calibration standards are used. It is also found that there is no need to determine the individual S-parameters of the test fixtures. In order to eliminate the problem of phase uncertainty, three different precise (known) reflection standards or one known reflection standard plus one known transmission standard should be used to calibrate symmetrical test fixtures. For the asymmetrical cases, three known standards, including at least one transmission standard, should be used. The thru-open-match (TOM) and thru-short-match (TSM) techniques are the simplest methods, and they have no bandwidth limitation. When the standards are imprecise (unknown), it is recommended to use any suitable technique, such as the thru-reflect-line, line-reflect-line, thru-short-delay, thru-open-delay,line-reflect-match, line-reflect-reflect-match, or multiline methods, to accurately determine the values of the required calibration terms and, in addition, to use the TOM or TSM method with the same imprecise standards to resolve the phase uncertainty.

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This paper begins from the thru-short-open (TSO) and thru-line-match (TLM) methods to investigate the correlation of the calibration equations of these two methods, The relations among the measurements with the corresponding standards are obtained. It is found that the line standard with zero length can be used instead of ideal open and short, in case that two test fixtures are symmetrical. For asymmetrical fixtures, the measurements with the standards line, open and short are related at certain frequencies, and the matched load can be replaced by the line standards. The relations established are used to test short and match standards and analyze the freqPuency limits of the TSO method, Good agreement between theory and experiment is obtained, It is found that the TSO method becomes very poor when the insertion phase of the thru standard is near n pi/4, and this method has a lower frequency limit. The TLM method is found unsuitable for calibrating asymmetrical fixtures.