Reduced swimming abilities in fast-growing transgenic common carp Cyprinus carpio associated with their morphological variations

Critical swimming speeds (U-crit) and morphological characters were compared between the F-4 generation of GH-transgenic common carp Cyprinus carpio and the non-transgenic controls. Transgenic fish displayed a mean absolute U-crit value 22.3% lower than the controls. Principal component analysis identified variations in body shape, with transgenic fish having significantly deeper head, longer caudal length of the dorsal region, longer standard length (L-S) and shallower body and caudal region, and shorter caudal length of the ventral region. Swimming speeds were related to the combination of deeper body and caudal region, longer caudal length of the ventral region, shallower head depth, shorter caudal length of dorsal region and L-S. These findings suggest that morphological variations which are poorly suited to produce maximum thrust and minimum drag in GH-transgenic C. carpio may be responsible for their lower swimming abilities in comparison with non-transgenic controls.

Fast-growing transgenic common carp mounfing compensatory growth

Compensatory growth is a phase of accelerated growth apparent when favourable conditions are restored after a period of growth depression. To investigate if F-2 common 'all-fish' growth hormone gene transgenic common carp (Cyprinus carpio) could mount compensatory growth, a 9 week study at 29 degrees C was performed. The control group was fed to satiation twice a day throughout the experiment. The other two groups were deprived of feed for 1 or 2 weeks, respectively, and then fed to satiation during the re-feeding period. At the end of the experiment, the live masses of fish in the deprived groups were still significantly lower than those of the controls. During the re-feeding period, size-adjusted mean specific growth rates and mean feed intakes were significantly higher in the deprived fish than in the controls, indicating a partial compensatory growth response in these fish. No significant differences were found in food conversion efficiency between the deprived and control fish during re-feeding, suggesting that hyperphagia was the mechanism responsible for increased growth rates. The proximate composition of the deprived fish at the end of the experiment was similar to that of the control fish. This study is, to our knowledge, the first to report that fast-growing transgenic fish can achieve partial compensation of growth following starvation. (c) 2007 The Authors Journal compilation (c) 2007 The Fisheries Society of the British Isles.

Application of fast Pade approximation in simulating photonic crystal nanocavities by FDTD technology

The exact calculation of mode quality factor Q is a key problem in the design of high-Q photonic crystal nanocavity. On the basis of further investigation on conventional Pade approximation, FDM and DFT, Pade approximation with Baker's algorithm is enhanced through introducing multiple frequency search and parabola interpolation. Though Pade approximation is a nonlinear signal processing method and only short time sequence is needed, we find the different length of sequence requirements for 2D and 3D FDTD, which is very important to obtain convergent and accurate results. By using the modified Pade approximation method and 3D FDTD, the 2D slab photonic crystal nanocavity is analyzed and high-Q multimode can be solved quickly instead of large range high-resolution scanning. Monitor position has also been investigated. These results are very helpful to the design of photonic crystal nanocavity devices. (C) 2008 Elsevier B.V. All rights reserved.

Compact non-binary fast adders using single-electron devices

This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.

Silicon-on-insulator thermo-optic variable attenuator module with fast response

A thermo-optic variable optical attenuator module composed of a silicon-on-insulator attenuator chip and driving circuit was designed and fabricated. The module exhibited a maximum attenuation of 21.8 dB and a response time of 10 mu s. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

Rearrangeable nonblocking SOI waveguide thermooptic 4x4 switch matrix with low insertion loss and fast response

A rearrangeable nonblocking 4 x 4 thermooptic silicon-on-insulator waveguide switch matrix at 1.55-mu m integrated spot size converters is designed and fabricated for the first time. The insertion losses and polarization-dependent losses of the four channels are less than 10 and 0.8 dB, respectively. The extinction ratios are larger than 20 dB. The response times are 4.6 mu s for rising edge and 1.9 mu s for failing edge.

A silicon-on-insulator-based thermo-optic waveguide switch with low insertion loss and fast response

A silicon-on-insulator-based thermo-optic waveguide switch integrated with spot size converters is designed and fabricated by inductively coupled plasma reactive ion etching. The device shows good characteristics, including low, insertion loss of 8 +/- 1 dB for wavelength 1530-1580 nm and fast response times of 4.6 As for rising edge and 1.9 mu s for failing edge. The extinction ratios of the two channels are 19.1 and 18 dB, respectively.

Fabrication and analysis of 2x2 thermo-optic SOI waveguide switch with low power consumption and fast response by anisotropy chemical etching

A low power consumption 2 x 2 thermo-optic switch with fast response was fabricated on silicon-on-insulator by anisotropy chemical etching. Blocking trenches were etched on both sides of the phase-shifting arms to shorten device length and reduce power consumption. Thin top cladding layer was grown to reduce power consumption and switching time. The device showed good characteristics, including a low switching power of 145 mW and a fast switching speed of 8 +/- 1 mus, respectively. Two-dimensional finite element method was applied to simulate temperature field in the phase-shifting arm instead of conventional one-dimensional method. According to the simulated result, a new two-dimensional index distribution of phase-shifting arm was determined. Consequently finite-difference beam propagation method was employed to simulate the light propagation in the switch, and calculate the power consumption as well as the switching speed. The experimental results were in good agreement with the theoretical estimations. (C) 2004 Elsevier B.V. All rights reserved.

Silicon-on-insulator-based waveguide switch with fast response

Based on thermo-optical effect of silicon, a 2 x 2 switch is fabricated in silicon-on-insulator by chemical etching. The switch presents an extinction ratio of 26 dB and a power consumption of 169 mW. The response time F similar to 10.5 mus.

Experimental study of a pulsed ytterbium-doped fibre laser with fast and slow saturable absorbers in a linear cavity

We present a linear-cavity stretched-pulse fibre laser with mode locking by a nonlinear polarization rotation and by semiconductor saturable-absorber mirrors. A Q-switched mode-locking cw train and a mode-locking pulse train are obtained in the experiment. We investigate the effects of the equivalent fast saturable absorber and the slow saturable absorbers in experiment. It is found that neither the nonlinear polarization evolution effect nor a semiconductor saturable absorber mirror is enough to produce the stable cw mode-locking pulses in this experiment. A nonlinear polarization evolution effect controls the cavity loss to literally carve the pulses; semiconductor saturable absorber mirrors provide the self-restarting and maintain the stability of the mode-locking operation.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Performing Fast Addition and Multiplication by Transferring Single Electrons

This paper proposes novel fast addition and multiplication circuits that are based on non-binary redundant number systems and single electron (SE) devices. The circuits consist of MOSFET-based single-electron (SE) turnstiles. We use the number of electrons to represent discrete multiple-valued logic states and we finish arithmetic operations by controlling the number of electrons transferred. We construct a compact PD2,3 adder and a 12x12bit multiplier using the PD2,3 adder. The speed of the adder can be as high as 600MHz with 400nW power dissipation. The speed of the adder is regardless of its operand length. The proposed circuits have much smaller transistors than conventional circuits.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.