Dielectric relaxation and giant dielectric constant of Nb-doped CaCu3Ti4O12 ceramics under dc bias voltage

CaCu3Ti(4-x)Nb(x)O(12) (x = 0, 0.01, 0.08, 0.2) ceramics were fabricated by a conventional solid-state reaction method. The ceramics showed the body-centered cubic structure without any foreign phases and the grain size decreases with Nb doping. Two Debye-type relaxations were observed for the Nb-doped samples at low frequency and high frequency, respectively. The complex electric modulus analysis revealed that the surface layer, grains and grain boundaries contributed to the dielectric constant. The low-frequency dielectric constant relative to the surface layer decreased to a minimum and then increased with the dc bias voltage at 100 Hz, which were well explained in terms of a model containing two metal oxide semiconductors in series, confirming the surface layer in the ceramics. The shift voltage V-B corresponding to the minimal capacitance increased with increase of the composition x. (C) 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Enhanced charge storage characteristics of silicon nanocrystals fabricated by electron-beam coevaporation of Si and SiOx(x=1 or 2)

In this article, a simple and flexible electron-beam coevaporation (EBCE) technique has been reported of fabrication of the silicon nanocrystals (Si NCs) and their application to the nonvolatile memory. For EBCE, the Si and SiOx(x=1 or 2) were used as source materials. Transmission electron microscopy images and Raman spectra measurement verified the formation of the Si NCs. The average size and area density of the Si NCs can be adjusted by increasing the Si:O weight ratio in source material, which has a great impact on the crystalline volume fraction of the deposited film and on the charge storage characteristics of the Si NCs. A memory window as large as 6.6 V under +/- 8 V sweep voltage was observed for the metal-oxide-semiconductor capacitor structure with the embedded Si NCs.

Silicon-on-insulating multi-layers for total-dose irradiation hardness

Silicon-on-insulating multi-layer (SOIM) materials were fabricated by co-implantation of oxygen and nitrogen ions with different energies and doses. The multilayer microstructure was investigated by cross-sectional transmission electron microscopy. P-channel metal-oxide-semiconductor (PMOS) transistors and metal-semiconductor-insulator-semiconductor (MSIS) capacitors were produced by these materials. After the irradiated total dose reaches 3 x 10(5) rad (Si), the threshold voltage of the SOIM-based PMOS transistor only shifts 0.07 V, while thin silicon-on-insulating buried-oxide SIMOX-based PMOS transistors have a shift of 1.2V, where SIMOX represents the separated by implanted oxygen. The difference of capacitance of the SOIM-based MSIS capacitors before and after irradiation is less than that of the thin-box SIMOX-based MSIS capacitor. The results suggest that the SOIM materials have a more remarkable irradiation tolerance of total dose effect, compared to the thin-buried-oxide SIMOX materials.

A novel technique for predicting ionizing radiation effects of commercial MOS devices

A nondestructive selection technique for predicting ionizing radiation effects of commercial metal-oxide-semiconductor (MOS) devices has been put forward. The basic principle and application details of this technique have been discussed. Practical application for the 54HC04 and 54HC08 circuits has shown that the predicted radiation-sensitive parameters such as threshold voltage, static power supply current and radiation failure total dose are consistent with the experimental results obtained only by measuring original electrical parameters. It is important and necessary to choose suitable information parameters. This novel technique can be used for initial radiation selection of some commercial MOS devices.

Radiation hardness improvement of separation-by-implantation-of-oxygen/silicon-on-insulator material by nitrogen ion implantation

In our work, nitrogen ions were implanted into separation-by-implantation-of-oxygen (SIMOX) wafers to improve the radiation hardness of the SIMOX material. The experiments of secondary ion mass spectroscopy (SIMS) analysis showed that some nitrogen ions were distributed in the buried oxide layers and some others were collected at the Si/SiO2 interface after annealing. The results of electron paramagnetic resonance (EPR) suggested the density of the defects in the nitrided samples changed with different nitrogen ion implantation energies. Semiconductor-insulator-semiconductor (SIS) capacitors were made on the materials, and capacitance-voltage (C-V) measurements were carried out to confirm the results. The super total dose radiation tolerance of the materials was verified by the small increase of the drain leakage current of the metal-oxide-semiconductor field effect transistor with n-channel (NMOSFETs) fabricated on the materials before and after total dose irradiation. The optimum implantation energy was also determined.

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

A study on the realization of radio frequency energy AC/DC charge pump based on MOS FET

This paper presents a novel efficient charge pump composed of low Vth metal-oxide-semiconductor (MOS) field effect transistors (FET) in the course of realizing radio frequency (RF) energy AC/DC conversion. The novel structure eliminates those defects caused by typical Schottky-diode charge pumps, which are dependent on specific processes and inconsistent in quality between different product batches. Our analyses indicate that an easy-fabricated, stable and efficient RF energy AC/DC charge pump can be conveniently implemented through reasonably configuring the MOS transistor aspect ratio, and other design parameters such as capacitance, multiplying stages to meet various demands on performance.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A novel vision chip for high-speed target tracking

This paper presents a novel vision chip for high-speed target tracking. Two concise algorithms for high-speed target tracking are developed. The algorithms include some basic operations that can be used to process the real-time image information during target tracking. The vision chip is implemented that is based on the algorithms and a row-parallel architecture. A prototype chip has 64 x 64 pixels is fabricated by 0.35 pm complementary metal-oxide-semiconductor transistor (CMOS) process with 4.5 x 2.5 mm(2) area. It operates at a rate of 1000 frames per second with 10 MHz chip main clock. The experiment results demonstrate that a high-speed target can be tracked in complex static background and a high-speed target among other high-speed objects can be tracked in clean background.

Quantum mechanical effects in nanometer field effect transistors

The atomistic pseudopotential quantum mechanical calculations for million atom nanosized metal-oxide-semiconductor field-effect transistors (MOSFETs) are presented. When compared with semiclassical Thomas-Fermi simulation results, there are significant differences in I-V curve, electron threshold voltage, and gate capacitance. In many aspects, the quantum mechanical effects exacerbate the problems encountered during device minimization, and it also presents different mechanisms in controlling the behaviors of a nanometer device than the classical one. (c) 2007 American Institute of Physics.

Novel hybrid voltage controlled ring oscillators using single electron and MOS transistors

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.

Silicon light emitting devices in CMOS technology

Two silicon light emitting devices with different structures are realized in standard 0.35 mu m complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6 nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/Cm-2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm..

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A high-performance Si-based MOS electrooptic phase modulator with a shunt-capacitor configuration

A novel Si-based metal-oxide-semiconductor (MOS) electrooptic phase modulator including two shunt oxide layer capacitors integrated on a silicon-on-insulator (SOI) waveguide is simulated and analyzed. The refractive index near the two gate oxide layers is modified by the free carrier dispersion effect induced by applying a positive bias on the electrodes. The theoretical calculation of free carrier distribution coupled with optical guided mode propagation characteristics has been carried out. The influence of the structure parameters such as the width and the doping level of the active region are analyzed. A half-wave voltage V-pi = 4 V is demonstrated with an 8-mm active region length and a 4-mu m width of an inner rib under an accumulation mode. When decreasing the inner rib width to 1 mu m, the phase modulation efficiency is even higher, and the rise and fall times reach 50 and 40 ps, respectively, with a 1.0 x 10(17) cm(-3) doping level in the active region.

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.