69 resultados para Standard map


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We have made a complete set of painting probes for the domestic horse by degenerate oligonucleotide-primed PCR amplification of flow-sorted horse chromosomes. The horse probes, together with a full set of those available for human, were hybridized onto metaphase chromosomes of human, horse and mule. Based on the hybridization results, we have generated genome-wide comparative chromosome maps involving the domestic horse, donkey and human. These maps define the overall distribution and boundaries of evolutionarily conserved chromosomal segments in the three genomes. Our results shed further light on the karyotypic relationships among these species and, in particular, the chromosomal rearrangements that underlie hybrid sterility and the occasional fertility of mules.

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Cross-species chromosome painting with probes derived from flow-sorted dog and human chromosomes was used to construct a high-resolution comparative map for the pig. In total 98 conserved autosomal segments between pig and dog were detected by probes specific for the 38 autosomes and X Chromosome of the dog. Further integration of our results with the published human-dog and cat-dog comparative maps, and with data from comparative gene mapping, increases the resolution of the current pig-human comparative map. It allows for the conserved syntenies detected in the pig, human, and cat to be aligned against the putative ancestral karyotype of eutherian mammals and for the history of karyotype evolution of the pig lineage to be reconstructed. Fifteen fusions, 17 fissions, and 23 inversions are required to convert the ancestral mammalian karyotype into the extant karyotype of the pig.

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Epigenetic regulation in insects may have effects on diverse biological processes. Here we survey the methylome of a model insect, the silkworm Bombyx mori, at single-base resolution using Illumina high-throughput bisulfite sequencing (MethylC-Seq). We conservatively estimate that 0.11% of genomic cytosines are methylcytosines, all of which probably occur in CG dinucleotides. CG methylation is substantially enriched in gene bodies and is positively correlated with gene expression levels, suggesting it has a positive role in gene transcription. We find that transposable elements, promoters and ribosomal DNAs are hypomethylated, but in contrast, genomic loci matching small RNAs in gene bodies are densely methylated. This work contributes to our understanding of epigenetics in insects, and in contrast to previous studies of the highly methylated genomes of Arabidopsis(1) and human(2), demonstrates a strategy for sequencing the epigenomes of organisms such as insects that have low levels of methylation.

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Male and female heroin-dependent patients (HDPs) matched with "normal" people were tested on 4 topographical orientation tasks: schematic map-following, map-memory, schematic picture-following, and picture-memory tasks. The results showed that, in general

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Genetic linkage maps were constructed for large yellow croaker Pseudosciaena crocea (Richardson, 1846) using AFLP and microsatellite markers in an F-1 family. Five hundred and twenty-three AFLP markers and 36 microsatellites were genotyped in the parents and 94 F-1 progeny. Among these, 362 AFLP markers and 13 SSR markers followed the 1:1 Mendelian segregation ratio (P > 0.05). The female genetic map contained 181 AFLP and 7 microsatellite markers forming 24 linkage groups spanning 2959.1 cM, while the male map consisted of 153 AFLP and 8 microsatellite markers in 23 linkage groups covering 2205.7 cM. One sex linked marker was mapped to the male map and co-segregated with the AFLP marker agacta355, suggesting an XY-male determination mechanism and this may be useful in the breeding of monosex populations. (c) 2007 Elsevier B.V. All rights reserved.

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National Natural Science Foundation of China 60536030 60776024 60877035 90820002 National High-Technology Research and Development Program of China 2007AA04Z329 2007AA04Z254

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A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 mu m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5V 10mA. The silicon dioxide waveguide is composed of multiple layers of silicon dioxide between different metals layers. A two PN-junctions photodetector composed of n-well/p-substrate junction and p(+) active implantation/n-well junction maximizes the depletion region width. The readout circuitry in pixels is exploited to handle as small as 0.1nA photocurrent. Simulation and testing results show that the optical emissions powers are about two orders higher than the low frequency detectivity of silicon CMOS photodetcctor and receiver circuit.

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In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a multi-standard (IEEE 802.11a/b/g and DVB-H) application and bandwidth (3MHz, 4MHz, 9.5MHz) is present. The filter exploits digitally-controlled polysilicon resister banks and an accurate automatic tuning scheme to account for process and temperature variations. The automatic frequency calibration scheme provides better than 3% corner frequency accuracy. The Butterworth filter is design for receiver (WLAN and DVB-H mode) and transmitter (WLAN mode). The filter dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from 2.85-V supply. The dissipation of calibration consumes 2mA. The circuit has been fabricated in a 0.35um 47-GHz SiGe BiCMOS technology, the receiver and transmitter occupy 0.28-mm(2) and 0.16-mm(2) (calibration circuit excluded), respectively.

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This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

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A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

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A 1GHz monolithic photo-detector (PD) and trans-impedance amplifier (TIA) is designed with the standard 0.35 mu m CMOS technique. The design of the photo-detector is analyzed and the CMOS trans-impedance amplifier is also analyzed in the paper. The integrating method is described too. The die photograph is also showed in the paper.

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A silicon light emitting device is designed and simulated. It is fabricated in 0.6 mum standard CMOS technology. The device can give more than 1 muW optical power of visible light under reverse breakdown. The device can be turned on at a bias of 0.88 V and work in a large range of voltage: 1.0-6.0 V The external electrical-optical conversion efficiency is more than 10(-6). The optical spectrum of the device is between 540-650 nm, which have a clear peak near 580 nm. The emission mechanism can be explained by a hot carrier direct recombination model.

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An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).