An analysis of expected delay reduction by replacing a congested at-grade intersection with an interchange.

Texas Department of Transportation, Austin

Automatic layout generation of static CMOS circuits targeting delay and power

The evolution of integrated circuits technologies demands the development of new CAD tools. The traditional development of digital circuits at physical level is based in library of cells. These libraries of cells offer certain predictability of the electrical behavior of the design due to the previous characterization of the cells. Besides, different versions of each cell are required in such a way that delay and power consumption characteristics are taken into account, increasing the number of cells in a library. The automatic full custom layout generation is an alternative each time more important to cell based generation approaches. This strategy implements transistors and connections according patterns defined by algorithms. So, it is possible to implement any logic function avoiding the limitations of the library of cells. Tools of analysis and estimate must offer the predictability in automatic full custom layouts. These tools must be able to work with layout estimates and to generate information related to delay, power consumption and area occupation. This work includes the research of new methods of physical synthesis and the implementation of an automatic layout generation in which the cells are generated at the moment of the layout synthesis. The research investigates different strategies of elements disposition (transistors, contacts and connections) in a layout and their effects in the area occupation and circuit delay. The presented layout strategy applies delay optimization by the integration with a gate sizing technique. This is performed in such a way the folding method allows individual discrete sizing to transistors. The main characteristics of the proposed strategy are: power supply lines between rows, over the layout routing (channel routing is not used), circuit routing performed before layout generation and layout generation targeting delay reduction by the application of the sizing technique. The possibility to implement any logic function, without restrictions imposed by a library of cells, allows the circuit synthesis with optimization in the number of the transistors. This reduction in the number of transistors decreases the delay and power consumption, mainly the static power consumption in submicrometer circuits. Comparisons between the proposed strategy and other well-known methods are presented in such a way the proposed method is validated.

Predicting delay reductions from freeway traffic diversion for incident management

Traffic incidents are a major source of traffic congestion on freeways. Freeway traffic diversion using pre-planned alternate routes has been used as a strategy to reduce traffic delays due to major traffic incidents. However, it is not always beneficial to divert traffic when an incident occurs. Route diversion may adversely impact traffic on the alternate routes and may not result in an overall benefit. This dissertation research attempts to apply Artificial Neural Network (ANN) and Support Vector Regression (SVR) techniques to predict the percent of delay reduction from route diversion to help determine whether traffic should be diverted under given conditions. The DYNASMART-P mesoscopic traffic simulation model was applied to generate simulated data that were used to develop the ANN and SVR models. A sample network that comes with the DYNASMART-P package was used as the base simulation network. A combination of different levels of incident duration, capacity lost, percent of drivers diverted, VMS (variable message sign) messaging duration, and network congestion was simulated to represent different incident scenarios. The resulting percent of delay reduction, average speed, and queue length from each scenario were extracted from the simulation output. The ANN and SVR models were then calibrated for percent of delay reduction as a function of all of the simulated input and output variables. The results show that both the calibrated ANN and SVR models, when applied to the same location used to generate the calibration data, were able to predict delay reduction with a relatively high accuracy in terms of mean square error (MSE) and regression correlation. It was also found that the performance of the ANN model was superior to that of the SVR model. Likewise, when the models were applied to a new location, only the ANN model could produce comparatively good delay reduction predictions under high network congestion level.

Predicting delay reductions from freeway traffic diversion for incident management

Traffic incidents are a major source of traffic congestion on freeways. Freeway traffic diversion using pre-planned alternate routes has been used as a strategy to reduce traffic delays due to major traffic incidents. However, it is not always beneficial to divert traffic when an incident occurs. Route diversion may adversely impact traffic on the alternate routes and may not result in an overall benefit. This dissertation research attempts to apply Artificial Neural Network (ANN) and Support Vector Regression (SVR) techniques to predict the percent of delay reduction from route diversion to help determine whether traffic should be diverted under given conditions. The DYNASMART-P mesoscopic traffic simulation model was applied to generate simulated data that were used to develop the ANN and SVR models. A sample network that comes with the DYNASMART-P package was used as the base simulation network. A combination of different levels of incident duration, capacity lost, percent of drivers diverted, VMS (variable message sign) messaging duration, and network congestion was simulated to represent different incident scenarios. The resulting percent of delay reduction, average speed, and queue length from each scenario were extracted from the simulation output. The ANN and SVR models were then calibrated for percent of delay reduction as a function of all of the simulated input and output variables. The results show that both the calibrated ANN and SVR models, when applied to the same location used to generate the calibration data, were able to predict delay reduction with a relatively high accuracy in terms of mean square error (MSE) and regression correlation. It was also found that the performance of the ANN model was superior to that of the SVR model. Likewise, when the models were applied to a new location, only the ANN model could produce comparatively good delay reduction predictions under high network congestion level.

Hierarchical fuzzy logic traffic control at a road junction

Traffic control at road junctions is one of the major concerns in most metropolitan cities. Controllers of various approaches are available and the required control action is the effective green-time assigned to each traffic stream within a traffic-light cycle. The application of fuzzy logic provides the controller with the capability to handle uncertain natures of the system, such as drivers’ behaviour and random arrivals of vehicles. When turning traffic is allowed at the junction, the number of phases in the traffic-light cycle increases. The additional input variables inevitably complicate the controller and hence slow down the decision-making process, which is critical in this real-time control problem. In this paper, a hierarchical fuzzy logic controller is proposed to tackle this traffic control problem at a 2-way road junction with turning traffic. The two levels of fuzzy logic controllers devise the minimum effective green-time and fine-tune it respectively at each phase of a traffic-light cycle. The complexity of the controller at each level is reduced with smaller rule-set. The performance of this hierarchical controller is examined by comparison with a fixed-time controller under various traffic conditions. Substantial delay reduction has been achieved as a result and the performance and limitation of the controller will be discussed.

The use of supply chain management to reduce delays : Malaysian public sector construction projects

Construction delays are a critical problem for Malaysian public sector projects. These delays have been blamed mainly on inefficient traditional construction practices that continue to dominate the current industry. This paper reports the progress to date of a Ph.D. research project aimed at developing a framework to utilize Supply Chain Management (SCM) tools to improve the time performance of Malaysian Government projects. The potential of SCM has been identified for public sector governance and its use in Malaysia is now being considered within the strategy of the Malaysian Construction Industry Master Plan (2006-2015). Encouraged by success in the UK, there is a cautious optimism concerning the successful application of SCM in Malaysia. This paper considers delay as a problem in Malaysian public sector projects, establishes the need to embrace SCM and then elucidates the need and strategies for the development of a delay reduction framework. A literature review, survey mechanism and structured interview schedule will be undertaken to achieve the research objectives. The final research outcome will be a framework that addresses root delay contributors (“pathogens”) and applies SCM tools for their mitigation.

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

O impacto da redução do custo do Brasil sobre a defasagem cambial

O objetivo deste trabalho é determinar qual o impacto da redução do custo Brasil sobre a defasagem cambial. Supõe-se uma economia em que o câmbio esteja fora de equilíbrio. A partir desta situação calcula-se o impacto de ganhos de eficiência e/ou redução de alíquotas de impostos distorcivos sobre o desequilíbrio cambial. O argumento básico é que em equilíbrio geral não é obrigatoriamente verdade que ganhos de eficiência concorram para reduzir o atraso cambial: é necessário saber em que setor e/ ou sob qual fator de produção a distorção incide. O principal resultado é que ganhos de produtividade no setor de bens comercializáveis reduzem o atraso cambial, no setor de bens domésticos elevam o atraso cambial, e se for em ambos os setores o resultado dependerá da resposta da demanda. Se a elasticidade renda da demanda do bem doméstico for maior do que a do bem comercializável o atraso cambial é reduzido. caso contrário eleva-se. Em particular quando a redução do custo Brasil significa elevação da eficiência do sistema portuário nada pode ser afirmado. Antes de responder esta questão, a segunda seção do trabalho discute o conceito de câmbio real, desequilíbrio cambial e de valorização cambial.

Impacto da redução do custo Brasil sobre a defasagem cambial

O objetivo deste trabalho é determinar qual o impacto da redução do custo Brasil sobre a defasagem cambial. Supõe-se uma economia em que o câmbio esteja fora de equilíbrio. A partir dessa situação, calcula-se o impacto de ganhos de eficiência e/ou redução de alíquotas de impostos distorcivos sobre o desequilíbrio cambial. O argumento básico é que, em equilíbrio geral, não é obrigatoriamente verdade que ganhos de eficiência concorram para reduzir o atraso cambial: é necessário saber em que setor e/ou sob qual fatorde produção a distorção incide. O principal resultado é que ganhos de produtividade no setor de bens comercializáveis reduzem o atraso cambial; no setor de bens domésticos, elevam o atraso cambial e, se for em ambos os setores, o resultado dependerá da resposta da demanda. Se a elasticidade-renda da demanda do bem doméstico for maior do que a do bem comercializável, o atraso cambial é reduzido, caso contrário, eleva-se. Em particular, quando a redução do custo Brasil significa elevação da eficiência do sistema portuário, nada pode ser afirmado. Antes de responder a esta questão, a segunda seção do trabalho discute o conceito de câmbio real,desequilíbrio cambial e valorização cambial.

An efficient reduction algorithm for computation of interconnect delay variability for statistical timing analysis in clock tree planning

In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect-networks in the presence of process variation. We develop a method for delay analysis of interconnects considering the impact of Gaussian metal process variations. The resistance and capacitance of a distributed RC line are expressed as correlated Gaussian random variables which are then used to compute the standard deviation of delay Probability Distribution Function (PDF) at all nodes in the interconnect network. Main objective is to find delay PDF at a cheaper cost. Convergence of this approach is in probability distribution but not in mean of delay. We validate our approach against SPICE based Monte Carlo simulations while the current method entails significantly lower computational cost.

Reduction in the use of diagnostic tests in infants with risk factors for early-onset neonatal sepsis does not delay antibiotic treatment.

Despite a low positive predictive value, diagnostic tests such as complete blood count (CBC) and C-reactive protein (CRP) are commonly used to evaluate whether infants with risk factors for early-onset neonatal sepsis (EOS) should be treated with antibiotics. We investigated the impact of implementing a protocol aiming at reducing the number of diagnostic tests in infants with risk factors for EOS in order to compare the diagnostic performance of repeated clinical examination with CBC and CRP measurement. The primary outcome was the time between birth and the first dose of antibiotics in infants treated for suspected EOS. Among the 11,503 infants born at ≥35 weeks during the study period, 222 were treated with antibiotics for suspected EOS. The proportion of infants receiving antibiotics for suspected EOS was 2.1% and 1.7% before and after the change of protocol (p = 0.09). Reduction of diagnostic tests was associated with earlier antibiotic treatment in infants treated for suspected EOS (hazard ratio 1.58; 95% confidence interval [CI] 1.20-2.07; p <0.001), and in infants with neonatal infection (hazard ratio 2.20; 95% CI 1.19-4.06; p = 0.01). There was no difference in the duration of hospital stay nor in the proportion of infants requiring respiratory or cardiovascular support before and after the change of protocol. Reduction of diagnostic tests such as CBC and CRP does not delay initiation of antibiotic treatment in infants with suspected EOS. The importance of clinical examination in infants with risk factors for EOS should be emphasised.

Displaced supracondylar humeral fractures: influence of delay of surgery on the incidence of open reduction, complications and outcome.

BACKGROUND Closed reduction and pinning is the accepted treatment choice for dislocated supracondylar humeral fractures in children (SCHF). Rates of open reduction, complications and outcome are reported to be dependent on delay of surgery. We investigated whether delay of surgery had influence on the incidence of open reduction, complications and outcome of surgical treatment of SCHFs in the authors' institution. METHODS Three hundred and forty-one children with 343 supracondylar humeral fractures (Gartland II: 144; Gartland III: 199) who underwent surgery between 2000 and 2009 were retrospectively analysed. The group consisted of 194 males and 149 females. The average age was 6.3 years. Mean follow-up was 6.2 months. Time interval between trauma and surgical intervention was determined using our institutional database. Clinical and radiographical data were collected for each group. Influence of delay of treatment on rates of open reduction, complications and outcome was calculated using logistic regression analysis. Furthermore, patients were grouped into 4 groups of delay (<6 h, n = 166; 6-12 h, n = 95; 12-24 h, n = 68; >24 h, n = 14) and the aforementioned variables were compared among these groups. RESULTS The incidence of open procedures in 343 supracondylar humeral fractures was 2.6 %. Complication rates were similar to the literature (10.8 %) primarily consisting of transient neurological impairments (9.0 %) which all were fully reversible by conservative treatment. Poor outcome was seen in 1.7 % of the patients. Delay of surgical treatment had no influence on rates of open surgery (p = 0.662), complications (p = 0.365) or poor outcome (p = 0.942). CONCLUSIONS In this retrospective study delay of treatment of SCHF did not have significant influence on the incidence of open reduction, complications, and outcome. Therefore, in SCHF with sufficient blood perfusion and nerve function, elective treatment is reasonable to avoid surgical interventions in the middle of the night which are stressful and wearing both for patients and for surgeons. LEVEL OF EVIDENCE III (retrospective comparative study).

Reduction of XPM penalty by sub-bit delay demodulation of DQPSK

We show that using a shortened delay in the demodulator for DQPSK channels can significantly reduce the XPM penalties caused by transmitting 40Gb/s DQPSK channels alongside 10Gb/s OOK channels. © 2010 Optical Society of America.

Reduction of XPM penalty by sub-bit delay demodulation of DQPSK

We show that using a shortened delay in the demodulator for DQPSK channels can significantly reduce the XPM penalties caused by transmitting 40Gb/s DQPSK channels alongside 10Gb/s OOK channels. © 2010 Optical Society of America.