The Columbian calculator : being a practical and concise system of decimal arithmetic : adapted to the use of schools in the United States /

Mode of access: Internet.

The five orders of architecture : containing the most plain and simple rules for drawing and executing them in the purest style, for the use of workmen : exhibiting the most approved modes of applying each in practice, suitably to the climate of Great Britain ; including an historical description of Gothic architecture, illustrated with specimens selected from the most celebrated structures now existing, and numerous plans, elevations, sections, and details of various buildings executed by architects of great eminence : to which are added treatises on projection, perspective, fractions, decimal arithmetic, &c. ...

Includes index.

Cost-Efficient Decimal Adder Design in Quantum-dot Cellular Automata

Applications that cannot tolerate the loss of accuracy that results from binary arithmetic demand hardware decimal arithmetic designs. Binary arithmetic in Quantum-dot cellular automata (QCA) technology has been extensively investigated in recent years. However, only limited attention has been paid to QCA decimal arithmetic. In this paper, two cost-efficient binary-coded decimal (BCD) adders are presented. One is based on the carry flow adder (CFA) using a conventional correction method. The other uses the carry look ahead (CLA) algorithm which is the first QCA CLA decimal adder proposed to date. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The proposed CFA-based BCD adder has the smallest area with the least number of cells. The proposed CLA-based BCD adder is the fastest with an increase in speed of over 60% when compared with the previous fastest decimal QCA adder. It also has the lowest overall cost with a reduction of over 90% when compared with the previous most cost-efficient design.

Design and synthesis of efficient mac architectures for high speed decimal processor

Most of the commercial and financial data are stored in decimal fonn. Recently, support for decimal arithmetic has received increased attention due to the growing importance in financial analysis, banking, tax calculation, currency conversion, insurance, telephone billing and accounting. Performing decimal arithmetic with systems that do not support decimal computations may give a result with representation error, conversion error, and/or rounding error. In this world of precision, such errors are no more tolerable. The errors can be eliminated and better accuracy can be achieved if decimal computations are done using Decimal Floating Point (DFP) units. But the floating-point arithmetic units in today's general-purpose microprocessors are based on the binary number system, and the decimal computations are done using binary arithmetic. Only few common decimal numbers can be exactly represented in Binary Floating Point (BF P). ln many; cases, the law requires that results generated from financial calculations performed on a computer should exactly match with manual calculations. Currently many applications involving fractional decimal data perform decimal computations either in software or with a combination of software and hardware. The performance can be dramatically improved by complete hardware DFP units and this leads to the design of processors that include DF P hardware.VLSI implementations using same modular building blocks can decrease system design and manufacturing cost. A multiplexer realization is a natural choice from the viewpoint of cost and speed.This thesis focuses on the design and synthesis of efficient decimal MAC (Multiply ACeumulate) architecture for high speed decimal processors based on IEEE Standard for Floating-point Arithmetic (IEEE 754-2008). The research goal is to design and synthesize deeimal'MAC architectures to achieve higher performance.Efficient design methods and architectures are developed for a high performance DFP MAC unit as part of this research.

A new look at reversible logic implementation of decimal adder

Reversibility plays a fundamental role when logic gates such as AND, OR, and XOR are not reversible. computations with minimal energy dissipation are considered. Hence, these gates dissipate heat and may reduce the life of In recent years, reversible logic has emerged as one of the most the circuit. So, reversible logic is in demand in power aware important approaches for power optimization with its circuits. application in low power CMOS, quantum computing and A reversible conventional BCD adder was proposed in using conventional reversible gates.

Performance Analysis of Reversible Fast Decimal Adders

This paper presents a performance analysis of reversible, fault tolerant VLSI implementations of carry select and hybrid decimal adders suitable for multi-digit BCD addition. The designs enable partial parallel processing of all digits that perform high-speed addition in decimal domain. When the number of digits is more than 25 the hybrid decimal adder can operate 5 times faster than conventional decimal adder using classical logic gates. The speed up factor of hybrid adder increases above 10 when the number of decimal digits is more than 25 for reversible logic implementation. Such highspeed decimal adders find applications in real time processors and internet-based applications. The implementations use only reversible conservative Fredkin gates, which make it suitable for VLSI circuits.

Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

The elements of arithmetic ... in which decimal and integral arithmetic are combined, and taught inductively, on the system of Pestalozzi. Part 1st [2d].

Mode of access: Internet.

Year 6 students' idiosyncratic notions of unitising, reunitising and regrouping decimal number places

Having flexible notions of the unit (e.g., 26 ones can be thought of as 2.6 tens, 1 ten 16 ones, 260 tenths, etc.) should be a major focus of elementary mathematics education. However, often these powerful notions are relegated to computations where the major emphasis is on "getting the right answer" thus procedural knowledge rather than conceptual knowledge becomes the primary focus. This paper reports on 22 high-performing students' reunitising processes ascertained from individual interviews on tasks requiring unitising, reunitising and regrouping; errors were categorised to depict particular thinking strategies. The results show that, even for high-performing students, regrouping is a cognitively complex task. This paper analyses this complexity and draws inferences for teaching.

Strategies for comparing decimal numbers with the same whole-number part

The strategies employed by 130 Grade 5 Brisbane students in comparing decimal numbers which have the same whole-number part were compared with those identified in similar studies conducted in the USA, France and Israel. Three new strategies were identified. Similar to USA results, the most common comparison errors stemmed from the incorrect whole-number strategy in which length is confused with size. The findings of this present study tend to support Resnick et al.’s (1989) hypothesis that the introduction of decimal-fraction recording before common-fraction recording seems to promote better comparison of decimal numbers.

Construction of multiplicative abstract schema for decimal-number numeration

This paper reports on an intervention study planned to help Year 6 students construct the multiplicative structure underlying decimal-number numeration. Three types of intervention were designed from a numeration model developed from a large study of 173 Year 6 students’ decimal-number knowledge. The study found that students could acquire multiplicative structure as an abstract schema if instruction took account of prior knowledge as informed by the model.

Place value, multiplicativity, reunitizing and effective classroom teaching of decimal numeration

Student understanding of decimal number is poor (e.g., Baturo, 1998; Behr, Harel, Post & Lesh, 1992). This paper reports on a study which set out to determine the cognitive complexities inherent in decimal-number numeration and what teaching experiences need to be provided in order to facilitate an understanding of decimal-number numeration. The study gave rise to a theoretical model which incorporated three levels of knowledge. Interview tasks were developed from the model to probe 45 students’ understanding of these levels, and intervention episodes undertaken to help students construct the baseline knowledge of position and order (Level 1 knowledge) and an understanding of multiplicative structure (Level 3 knowledge). This paper describes the two interventions and reports on the results which suggest that helping students construct appropriate mental models is an efficient and effective teaching strategy.