Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

This paper proposes a drain current model for triple-gate n-type junctionless nanowire transistors. The model is based on the solution of the Poisson equation. First, the 2-D Poisson equation is used to obtain the effective surface potential for long-channel devices, which is used to calculate the charge density along the channel and the drain current. The solution of the 3-D Laplace equation is added to the 2-D model in order to account for the short-channel effects. The proposed model is validated using 3-D TCAD simulations where the drain current and its derivatives, the potential, and the charge density have been compared, showing a good agreement for all parameters. Experimental data of short- channel devices down to 30 nm at different temperatures have been also used to validate the model.

An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices

Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time consuming and cumbersome task. However, it is mandatory to have accurate device simulation, with good correlation with experimental results of strained devices, allowing for in-depth physical insight as well as prediction on the stress impact on the device electrical characteristics. This work proposes the use of an analytic function, based on the literature, to describe accurately the strain dependence on both channel length and fin width in order to simulate adequately strained triple-gate devices. The maximum transconductance and the threshold voltage are used as the key parameters to compare simulated and experimental data. The results show the agreement of the proposed analytic function with the experimental results. Also, an analysis on the threshold voltage variation is carried out, showing that the stress affects the dependence of the threshold voltage on the temperature. (C) 2011 Elsevier Ltd. All rights reserved.

Behavior of triple-gate Bulk FinFETs with and without DTMOS operation

In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance. Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristic; and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications. (C) 2011 Elsevier Ltd. All rights reserved.

Analysis of temperature variation influence on the analog performance of 45 degrees rotated triple-gate nMuGFETs

This work presents the analog performance of n-type triple-gate MuGFETs with high-k dielectrics and TiN gate material fabricated in 45 degrees rotated SOI substrates comparing their performance with standard MuGFETs fabricated without substrate rotation. Different fin widths are studied for temperatures ranging from 250 K up to 400 K. The results of transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and unit-gain frequency are studied. It is observed that the substrate rotation improves the carrier mobility of narrow MuGFETs at any temperature because of the changing in the conduction plane at the sidewalls from (1 1 0) to (1 0 0). For lower temperatures, the improvement of the carrier mobility of rotated MuGFETs is more noticeable as well as the rate of mobility improvement with the temperature decrease is larger. The output conductance is weakly affected by the substrate rotation. Although this improvement in the transconductance of rotated MuGFETs is negligibly transferred to the intrinsic voltage gain, the unity-gain frequency of rotated device is improved due to the larger carrier mobility in the entire range of temperatures studied. (C) 2011 Elsevier Ltd. All rights reserved.

Simulations of parasitic and intrinsic capacitances related to Multiple-Gate-Field-Effect Transistor architectures

Report for the scientific sojourn carried out at the Université Catholique de Louvain, Belgium, from March until June 2007. In the first part, the impact of important geometrical parameters such as source and drain thickness, fin spacing, spacer width, etc. on the parasitic fringing capacitance component of multiple-gate field-effect transistors (MuGFET) is deeply analyzed using finite element simulations. Several architectures such as single gate, FinFETs (double gate), triple-gate represented by Pi-gate MOSFETs are simulated and compared in terms of channel and fringing capacitances for the same occupied die area. Simulations highlight the great impact of diminishing the spacing between fins for MuGFETs and the trade-off between the reduction of parasitic source and drain resistances and the increase of fringing capacitances when Selective Epitaxial Growth (SEG) technology is introduced. The impact of these technological solutions on the transistor cut-off frequencies is also discussed. The second part deals with the study of the effect of the volume inversion (VI) on the capacitances of undoped Double-Gate (DG) MOSFETs. For that purpose, we present simulation results for the capacitances of undoped DG MOSFETs using an explicit and analytical compact model. It monstrates that the transition from volume inversion regime to dual gate behaviour is well simulated. The model shows an accurate dependence on the silicon layer thickness,consistent withtwo dimensional numerical simulations, for both thin and thick silicon films. Whereas the current drive and transconductance are enhanced in volume inversion regime, our results show thatintrinsic capacitances present higher values as well, which may limit the high speed (delay time) behaviour of DG MOSFETs under volume inversion regime.

Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects

Fin field effect transistors (FinFETS) are silicon-on-insulator (SOI) transistors with three-dimensional structures. As a result of some fabrication-process limitations (as nonideal anisotropic overetch) some FinFETs have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections, as expected. This geometric alteration results in some device issues, like carrier profile, threshold voltage, and corner effects. This work analyzes these consequences based on three-dimensional numeric simulation of several dual-gate and triple-gate FinFETs. The simulation results show that the threshold voltage depends on the sidewall inclination angle and that this dependence varies according to the body doping level. The corner effects also depend on the inclination angle and doping level. (C) 2008 The Electrochemical Society.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W(fin)) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. (C) 2011 Elsevier Ltd. All rights reserved.

Impact of SEG on uniaxially strained MuGFET performance

This work focuses on the impact of the source and drain Selective Epitaxial Growth (SEG) on the performance of uniaxially strained MuGFETs. With the channel length reduction, the normalized transconductance (gm.L./W) of unstressed MuGFETs decreases due to the series resistance and short channel effects (SCE), while the presence of uniaxial strain improves the gm. The competition between the series resistance (R(s)) and the uniaxial strain results in a normalized gm maximum point for a specific channel length. Since the SEG structure influences both R(s) and the strain in the channel, this work studies from room down to low temperature how these effects influence the performance of the triple-gate FETs. For lower temperatures, the strain-induced mobility enhancement increases and leads to a shift in the maximum point towards shorter channel lengths for devices without SEG. This shift is not observed for devices with SEG where the strain level is much lower. At 150 K the gm behavior of short channel strained devices with SEG is similar to the non SEC ones due to the better gm temperature enhancement for devices without SEG caused by the strain. For lower temperatures SEG structure is not useful anymore. (C) 2011 Elsevier Ltd. All rights reserved.

Temperature impact on the tunnel fet off-state current components

In this work, the temperature impact on the off-state current components is analyzed through numerical simulation and experimentally. First of all, the band-to-band tunneling is studied by varying the underlap in the channel/drain junction, leading to an analysis of the different off-state current components. For pTFET devices, the best behavior for off-state current was obtained for higher values of underlap (reduced BTBT) and at low temperatures (reduced SRH and TAT). At high temperature, an unexpected off-state current occurred due to the thermal leakage current through the drain/channel junction. Besides, these devices presented a good performance when considering the drain current as a function of the drain voltage, making them suitable for analog applications. (C) 2012 Elsevier Ltd. All rights reserved.

Photodetection with gate-controlled lateral BJTs from standard CMOS technology

The silicon-based gate-controlled lateral bipolar junction transistor (BJT) is a controllable four-terminal photodetector with very high responsivity at low-light intensities. It is a hybrid device composed of a MOSFET, a lateral BJT, and a vertical BJT. Using sufficient gate bias to operate the MOS transistor in inversion mode, the photodetector allows for increasing the photocurrent gain by 106 at low light intensities when the base-emitter voltage is smaller than 0.4 V, and BJT is off. Two operation modes, with constant voltage bias between gate and emitter/source terminals and between gate and base/body terminals, allow for tuning the photoresponse from sublinear to slightly above linear, satisfying the application requirements for wide dynamic range, high-contrast, or linear imaging. MOSFETs from a standard 0.18-μm triple-well complementary-metal oxide semiconductor technology with a width to length ratio of 8 μm /2 μm and a total area of ∼ 500μm2 are used. When using this area, the responsivities are 16-20 kA/W. © 2001-2012 IEEE.

Microbial Evaluation Of Traumatized Teeth Treated With Triple Antibiotic Paste Or Calcium Hydroxide With 2% Chlorhexidine Gel In Pulp Revascularization.

Revascularization outcome depends on microbial elimination because apical repair will not happen in the presence of infected tissues. This study evaluated the microbial composition of traumatized immature teeth and assessed their reduction during different stages of the revascularization procedures performed with 2 intracanal medicaments. Fifteen patients (7-17 years old) with immature teeth were submitted to the revascularization procedures; they were divided into 2 groups according to the intracanal medicament used: TAP group (n = 7), medicated with a triple antibiotic paste, and CHP group (n = 8), dressed with calcium hydroxide + 2% chlorhexidine gel. Samples were taken before any treatment (S1), after irrigation with 6% NaOCl (S2), after irrigation with 2% chlorhexidine (S3), after intracanal dressing (S4), and after 17% EDTA irrigation (S5). Cultivable bacteria recovered from the 5 stages were counted and identified by means of polymerase chain reaction assay (16S rRNA). Both groups had colony-forming unit counts significantly reduced after S2 (P < .05); however, no significant difference was found between the irrigants (S2 and S3, P = .99). No difference in bacteria counts was found between the intracanal medicaments used (P = .95). The most prevalent bacteria detected were Actinomyces naeslundii (66.67%), followed by Porphyromonas endodontalis, Parvimonas micra, and Fusobacterium nucleatum, which were detected in 33.34% of the root canals. An average of 2.13 species per canal was found, and no statistical correlation was observed between bacterial species and clinical/radiographic features. The microbial profile of infected immature teeth is similar to that of primarily infected permanent teeth. The greatest bacterial reduction was promoted by the irrigation solutions. The revascularization protocols that used the tested intracanal medicaments were efficient in reducing viable bacteria in necrotic immature teeth.

Primary Relapse Site Pattern In Women With Triple-negative Breast Cancer.

Despite the remarkable improvements in breast cancer (BC) characterization, accurate prediction of BC clinical behavior is often still difficult to achieve. Some studies have investigated the association between the molecular subtype, namely the basal-like BC and the pattern of relapse, however only few investigated the association between relapse pattern and immunohistochemical defined triple-negative breast cancers (TNBCs). The aim of this study was to evaluate the pattern of relapse in patients with TNBC, namely the primary distant relapse site. One-hundred twenty nine (129) invasive breast carcinomas with follow-up information were classified according to the molecular subtype using immunohistochemistry for ER, PgR and Her2. The association between TNBC and distant relapse primary site was analyzed by logistic regression. Using multivariate logistic regression analysis patients with TNBC displayed only 0.09 (95% CI: 0.00-0.74; p=0.02) the odds of the non-TNBC patients of developing bone primary relapse. Regarding visceral and lymph-node relapse, no differences between in this cohort were found. Though classically regarded as aggressive tumors, TNBCs rarely development primary relapse in bone when compared to non-TNBC, a clinical relevant fact when investigating a metastasis of an occult or non-sampled primary BC.