Experimental study on heavy ion single event effects in SOI SRAMs

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened military and space applications. The use of SOI has been motivated by the full dielectric isolation of individual transistors, which prevents latch-up. The sensitive region for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single event upset (SEU). In this study, 64 kB SOI SRAMs were exposed to different heavy ions, such as Cu, Br, I, Kr. Experimental results show that the heavy ion SEU threshold linear energy transfer (LET) in the 64 kB SOI SRAMs is about 71.8 MeV cm(2)/mg. Accorded to the experimental results, the single event upset rate (SEUR) in space orbits were calculated and they are at the order of 10(-13) upset/(day bit).

Designing single event upset mitigation techniques for large SRAM-Based FPGA components

This thesis presents the study and development of fault-tolerant techniques for programmable architectures, the well-known Field Programmable Gate Arrays (FPGAs), customizable by SRAM. FPGAs are becoming more valuable for space applications because of the high density, high performance, reduced development cost and re-programmability. In particular, SRAM-based FPGAs are very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. SRAM-based FPGA and micro-controllers represent a wide range of components in space applications, and as a result will be the focus of this work, more specifically the Virtex® family from Xilinx and the architecture of the 8051 micro-controller from Intel. The Triple Modular Redundancy (TMR) with voters is a common high-level technique to protect ASICs against single event upset (SEU) and it can also be applied to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based on counters. Faults were injected in all sensitive parts of the FPGA and a detailed analysis of the effect of a fault in a TMR design synthesized in the Virtex® platform was performed. Results from fault injection and from a radiation ground test facility showed the efficiency of the TMR for the related case study circuit. Although TMR has showed a high reliability, this technique presents some limitations, such as area overhead, three times more input and output pins and, consequently, a significant increase in power dissipation. Aiming to reduce TMR costs and improve reliability, an innovative high-level technique for designing fault-tolerant systems in SRAM-based FPGAs was developed, without modification in the FPGA architecture. This technique combines time and hardware redundancy to reduce overhead and to ensure reliability. It is based on duplication with comparison and concurrent error detection. The new technique proposed in this work was specifically developed for FPGAs to cope with transient faults in the user combinational and sequential logic, while also reducing pin count, area and power dissipation. The methodology was validated by fault injection experiments in an emulation board. The thesis presents comparison results in fault coverage, area and performance between the discussed techniques.

Single event molecular signalling for estimation and control

Cell biology is characterised by low molecule numbers and coupled stochastic chemical reactions with intrinsic noise permeating and dominating the interactions between molecules. Recent work [9] has shown that in such environments there are hard limits on the accuracy with which molecular populations can be controlled and estimated. These limits are predicated on a continuous diffusion approximation of the target molecule (although the remainder of the system is non-linear and discrete). The principal result of [9] assumes that the birth rate of the signalling species is linearly dependent on the target molecule population size. In this paper, we investigate the situation when the entire system is kept discrete, and arbitrary non-linear coupling is allowed between the target molecule and downstream signalling molecules. In this case it is possible, by relying solely on the event triggered nature of control and signalling reactions, to define non-linear reaction rate modulation schemes that achieve improved performance in certain parameter regimes. These schemes would not appear to be biologically relevant, raising the question of what are an appropriate set of assumptions for obtaining biologically meaningful results. © 2013 EUCA.

Improving Near-Miss Event Detection Rate at Railway Level Crossings

Even though crashes between trains and road users are rare events at railway level crossings, they are one of the major safety concerns for the Australian railway industry. Nearmiss events at level crossings occur more frequently, and can provide more information about factors leading to level crossing incidents. In this paper we introduce a video analytic approach for automatically detecting and localizing vehicles from cameras mounted on trains for detecting near-miss events. To detect and localize vehicles at level crossings we extract patches from an image and classify each patch for detecting vehicles. We developed a region proposals algorithm for generating patches, and we use a Convolutional Neural Network (CNN) for classifying each patch. To localize vehicles in images we combine the patches that are classified as vehicles according to their CNN scores and positions. We compared our system with the Deformable Part Models (DPM) and Regions with CNN features (R-CNN) object detectors. Experimental results on a railway dataset show that the recall rate of our proposed system is 29% higher than what can be achieved with DPM or R-CNN detectors.

Polycrystal versus single-crystal strain rate sensitivity of cadmium

Taking polycrystalline cadmium as an example and by utilizing the predicted temperature or strain rate-dependence of the (Hall-Petch) stress-grain size parameters, a reasonably quantitative explanation is given for the grain size dependence of apparent activation volume measurements. The explanation involves the theoretical relation of these measurements to single-crystal measurements.

Controlled spillover in a single catalyst pellet: Rate modification, mechanism and relationship with electrochemical promotion

The effect of spillover processes on the activity of a catalyst system consisting of a mixed oxygen ion and electronic conducting support La0.6Sr0.4Co0.2Fe0.8O3d and a metal catalyst (Pt) were investigated. Two types of model single-pellet catalysts were used employing Pt deposited on both sides of a dense LSCF disc pellet. One of these single pellets employed highly disperse, physically non-continuous Pt, in contrast to studies on electrochemical promotion, while the other used a low dispersion continuous film. Driving forces for promoter migration were controlled through the manipulation of the oxygen chemical potential difference across the membrane. Catalyst rate modification was observed in all cases. However, it was found that there is a complex relationship between the rate modification, the driving forces for spillover and the geometrical arrangement of the catalyst on the support (i.e. catalyst dispersion).

A Methodology to Emulate Single Event Upsets in Flip-Flops using FPGAs through Partial Reconfiguration and Instrumentation

This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the FFs. The method proposed in this paper is a hybrid approach that combines FPGA partial reconfiguration and extra logic added to the circuit under test, without modifying its operation. This approach has been integrated into a fault-injection platform, named NESSY (Non intrusive ErrorS injection SYstem), developed by our research group. Finally, this paper includes results on a Virtex-5 FPGA demonstrating the validity of the method on the ITC’99 benchmark set and a Feed-Forward Equalization (FFE) filter. In comparison with other approaches in the literature, this methodology reduces the resource consumption introduced to carry out the fault injection in FFs, at the cost of adding very little time overhead (1.6 �μs per fault).

SEU ground and flight data in static random access memories

This paper presents the vulnerabilities of single event effects (SEEs) simulated by heavy ions on ground and observed oil SJ-5 research satellite in space for static random access memories (SRAMs). A single event upset (SEU) prediction code has been used to estimate the proton-induced upset rates based oil the ground test curve of SEU cross-section versus heavy ion linear energy transfer (LET). The result agrees with that of the flight data.

Magnetic Flip Flops for Space Applications

The radiation environment of space presents a significant threat to the reliability of nonvolatile memory technologies. Ionizing radiation disturbs the charge stored on floating gates, and cosmic rays can permanently damage thin oxides. A new memory technology based on the magnetic tunneling junction (MTJ) appears to offer superior resistance to radiation effects and virtually unlimited write endurance. A magnetic flip flop has a number of potential applications, such as the configuration memory in field-programmable logic devices. However, using MTJs in a flip flop requires radically different circuitry for storing and retrieving data. New techniques are needed to insure that magnetic flip flops are reliable in the radiation environment of space. We propose a new radiation-tolerant magnetic flip flop that uses the inherent resistance of the MTJ to increase its immunity to single event upset and employs a robust “Pac-man” magnetic element.

Nessy 7.0: entorno de inyección de fallos para Artix-7

El hardware reconfigurable es una tecnología emergente en aplicaciones espaciales.Debido a las características de este hardware, pues su configuración lógica queda almacenada en memoria RAM estática, es susceptible de diversos errores que pueden ocurrir con mayor frecuencia cuando es expuesta a entornos de mayor radiación, como en misiones de exploración espacial. Entre estos se encuentran los llamados SEU o Single Event Upset, y suelen ser generados por partículas cósmicas, pues pueden tener la capacidad de descargar un transistor y de este modo alterar un valor lógico en memoria, y por tanto la configuración lógica del circuito. Por ello que surge la necesidad de desarrollar técnicas que permitan estudiar las vulnerabilidades de diversos circuitos, de forma económica y rápida, además de técnicas de protección de los mismos. En este proyecto nos centraremos en desarrollar una herramienta con este propósito, Nessy 7.0. La plataforma nos permitirá emular, detectar y analizar posibles errores causados por la radiación en los sistemas digitales. Para ello utilizaremos como dispositivo controlador, una Raspberry Pi 3, que contendrá la herramienta principal, y controlará y se comunicará con la FPGA que implementará el diseño a testear, en este caso una placa Nexys 4 DDR con una FPGA Artix-7. Finalmente evaluaremos un par de circuitos con la plataforma.