A method of extracting switching loss from a high efficiency MOSFET based half bridge converter

The measurement of losses in high efficiency / high power converters is difficult. Measuring the losses directly from the difference between the input and output power results in large errors. Calorimetric methods are usually used to bypass this issue but introduce different problems, such as, long measurement times, limited power loss measurement range and/or large set up cost. In this paper the total losses of a converter are measured directly and switching losses are exacted. The measurements can be taken with only three multimeters and a current probe and a standard bench power supply. After acquiring two or three power loss versus output current sweeps, a series of curve fitting processes are applied and the switching losses extracted.

An isolated MOSFET gate driver

Traditional methods of isolated MOSFET/IGBT gate drive are presented, and their pros and cons assessed. The best options are chosen to meet our objective— a small, high speed, low cost, low power isolated gate drive module. Two small ferrite bead transformers are used for isolation, one transmits power at 2.5MHz, the other sends narrow set reset pulses. On the secondary these pulses drive a transistor totem pole to ensure high current drive, and the value is held by CMOS buffers with positive feedback. An alternative design for driving logic level devices uses only an HC buffer on the secondary. Double sided SMDconstruction (primary one side, secondary on the other) yields an upright module 40x18x5mm. Propagation delaywas 20ns, and rise/fall time 15ns with a 1nF load. The design places no limits on frequency of operation or duty cycle. Power supply requirementswere 5V@20mA for operation below 100kHz, dominated by magnetising current.

Unified large and small signal non-quasi-static model for long channel symmetric DG MOSFET

We propose a unified model for large signal and small signal non-quasi-static analysis of long channel symmetric double gate MOSFET. The model is physics based and relies only on the very basic approximation needed for a charge-based model. It is based on the EKV formalism Enz C, Vittoz EA. Charge based MOS transistor modeling. Wiley; 2006] and is valid in all regions of operation and thus suitable for RF circuit design. Proposed model is verified with professional numerical device simulator and excellent agreement is found. (C) 2010 Elsevier Ltd. All rights reserved.

A Non Quasi-Static Small Signal Model for Long Channel Symmetric DG MOSFET

We propose a compact model for small signal non quasi static analysis of long channel symmetric double gate MOSFET The model is based on the EKV formalism and is valid in all regions of operation and thus suitable for RF circuit design Proposed model is verified with professional numerical device simulator and excellent agreement is found well beyond the cut-off frequency

Analytical modeling of quantum threshold voltage for triple gate MOSFET

In this work a physically based analytical quantum threshold voltage model for the triple gate long channel metal oxide semiconductor field effect transistor is developed The proposed model is based on the analytical solution of two-dimensional Poisson and two-dimensional Schrodinger equation Proposed model is extended for short channel devices by including semi-empirical correction The impact of effective mass variation with film thicknesses is also discussed using the proposed model All models are fully validated against the professional numerical device simulator for a wide range of device geometries (C) 2010 Elsevier Ltd All rights reserved

Large-Signal Model for Independent DG MOSFET

In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal-oxide-semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends.

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface.

Effect of scaling on the non-quasi-static behaviour of the MOSFET for RF ICs

The effect of scaling (1 μm to 0.09 μm) on the non-quasi-static (NQS) behaviour of the MOSFET has been studied using process and device simulation. It is shown that under fixed gate (Vgs) and drain (Vds) bias voltages, the NQS transition frequency (fNQS) scales as 1/Leff rather than 1/L2eff due to the velocity saturation effect. However, under the practical scaling guidelines, considering the scaling of supply voltage as well, fNQS shows a turn around effect at the sub 100 nm regime. The relation between unity gain frequency (ft) and fNQS is also evaluated and it is shown that ft and fNQS have similar trends with scaling.

Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET

A robust numerical solution of the input voltage equations (IVEs) for the independent-double-gate metal-oxide-semiconductor field-effect transistor requires root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of nonremovable discontinuity and singularity. In this brief, we do an exhaustive study of the different RBMs available in the literature and propose a single derivative-free RBM that could be applied to both trigonometric and hyperbolic IVEs and offers faster convergence than the earlier proposed hybrid NR-Ridders algorithm. We also propose some adjustments to the solution space for the trigonometric IVE that leads to a further reduction of the computation time. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric IVE and about 15% for hyperbolic IVE, by implementing the proposed algorithm in a commercial circuit simulator through the Verilog-A interface and simulating a variety of circuit blocks such as ring oscillator, ripple adder, and twisted ring counter.

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.

Bipolar Poisson Solution for Independent Double-Gate MOSFET

We propose a new set of input voltage equations (IVEs) for independent double-gate MOSFET by solving the governing bipolar Poisson equation (PE) rigorously. The proposed IVEs, which involve the Legendre's incomplete elliptic integral of the first kind and Jacobian elliptic functions and are valid from accumulation to inversion regimes, are shown to have good agreement with the numerical solution of the same PE for all bias conditions.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Performance Analysis of Strained Monolayer MoS2 MOSFET

We present a computational study on the impact of tensile/compressive uniaxial (epsilon(xx)) and biaxial (epsilon(xx) = epsilon(yy)) strain on monolayer MoS2, n-, and p-MOSFETs. The material properties like band structure, carrier effective mass, and the multiband Hamiltonian of the channel are evaluated using the density functional theory. Using these parameters, self-consistent Poisson-Schrodinger solution under the nonequilibrium Green's function formalism is carried out to simulate the MOS device characteristics. 1.75% uniaxial tensile strain is found to provide a minor (6%) ON current improvement for the n-MOSFET, whereas same amount of biaxial tensile strain is found to considerably improve the p-MOSFET ON currents by 2-3 times. Compressive strain, however, degrades both n-MOS and p-MOS devices performance. It is also observed that the improvement in p-MOSFET can be attained only when the channel material becomes indirect gap in nature. We further study the performance degradation in the quasi-ballistic long-channel regime using a projected current method.